National Technology Roadmap For Semiconductors Research Articles

Lithography for enabling advances in integrated circuits and devices

Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.

Thickness-dependent thermal reliability of low-dielectric constant polycrystalline PTFE submicron dielectric thin films

According to the SIA National Technology Roadmap for Semiconductors, interlevel dielectrics (ILDs) with a relative dielectric constant less than two will be needed for future integrated circuit devices beyond 0.1 μm generation. For possible low-dielectric constant (low- k) candidates with a relative dielectric constant less than two, polytetrafluoroethylene (PTFE) has the lowest dielectric constant among nonporous low- k materials, and thus is a strong future ILD candidate. As the feature size decreases, the ILD thickness is also expected to decrease. Thus needs exist for characterizing and understanding the possible thickness-induced thermal reliability of PTFE thin films for deep-submicron multilevel interconnection applications. The majority of low-dielectric constant candidates for ULSI ILD applications are amorphous polymers; techniques exist for characterizing the glass transition temperatures of amorphous polymers, which is the critical measure of their thermal stability. However, a simple but reliable method remained to be introduced for characterizing the thermal stability of submicron crystalline thin films such as PTFE. It is determined in the present work that the directly measured ellipsometric angles Δ and ψ can be used for detecting the solid↔liquid transition temperatures of on-wafer polycrystalline thin films. The novel approach is applied for investigating the solid↔liquid transitions of on-wafer PTFE thin films. The results show that the solid–liquid transitions depend on the film thickness as a result of film/surface, film/substrate interactions and the thickness-dependent crystal size. The results can be well described by modifying a previous model for size dependent solid–liquid transitions of nanocrystals.

Roadmap: Frontiers of Analytical Metrology for the Silicon Semiconductor Industry

Abstract The 1997 National Technology Roadmap for Semiconductors (NTRS) and the 1999 International Technology Roadmap for Semiconductors (ITRS) include chapters outlining metrology needs for the silicon semiconductor industry during the next five years and beyond1. The grand challenges include affordable scaling, new materials and structures, and yield and reliability. Although additional requirements within these categories are detailed, it is often difficult for the analytical specialist or metrology equipment vendor to translate these grand challenges into detailed and meaningful roadmaps for success in analytical applications or instrument development. The path-to-impact of a single metrology activity is not always clear.

Analysis of leakage currents and impact on off-state power consumption for CMOS technology in the 100-nm regime

Off-state leakage currents have been investigated for sub-100 nm CMOS technology. The two leakage mechanisms investigated in this work include conventional off-state leakage due to short channel effects and gate leakage through ultrathin gate oxides. The conventional off-state leakage due to short channel effects exhibited the similar characteristics as previously published; however, gate leakage introduces two significant consequences with respect to off-state power consumption: (1) an increase in the number of transistors contributing to the total off-state power consumption of the chip and (2) an increase in the conventional off-state current due to gate leakage near the drain region of the device. Using experimentally measured data, it is estimated that gate leakage does not exceed the off-state specifications of the National Technology Roadmap for Semiconductors for gate oxides as thin as 1.4 to 1.5 nm for high performance CMOS. Low power and memory applications may be limited to an oxide thickness of 1.8 to 2.0 nm in order to minimize the off-state power consumption and maintain an acceptable level of charge retention. The analysis in this work suggests that reliability will probably limit silicon oxide scaling for high performance applications whereas gate leakage will limit gate oxide scaling for low power and memory applications.

A minimum total power methodology for projecting limits on CMOS GSI

A circuit design methodology minimizing total power drain of a static complementary metal-oxide-semiconductor (CMOS) random logic network for a prescribed performance, operating temperature range, and short channel threshold voltage rolloff is investigated. Physical, continuous, smooth, and compact "transregional" MOSFET drain current models that consider high-field effects in scaled devices and permit tradeoffs between saturation drive current and subthreshold leakage current are employed to model CMOS circuit performance and power dissipation at low voltages. Transregional models are used in conjunction with physical short channel MOSFET threshold voltage rolloff models and stochastic interconnect distributions to project optimal supply voltages, threshold voltages, and device channel widths minimizing total power dissipated by CMOS logic circuits for each National Technology Roadmap for Semiconductors (NTRS) technology generation. Optimum supply voltage, corresponding to minimum total power dissipation, is projected to scale to 510 mV for the 50-nm 10-GHz CMOS generation in the year 2012. Techniques exploiting datapath parallelism to further scale the supply voltage are shown to offer decreasing reductions in power dissipation with technology scaling.

A global wiring paradigm for deep submicron design

Global interconnect is commonly regarded as a key potential bottleneck to the advancing performance of high-speed integrated circuits. Our previous work has suggested that local interconnect effects can be managed through a deep submicron design hierarchy that uses 50000 to 100000 gate modules as primitive building blocks. The primary goal of this paper is to examine global interconnect effects, within such a design hierarchy, to determine if there are any significant roadblocks which will prevent National Technology Roadmap for Semiconductors (NTRS) performance expectations from being met. Specifically, the issues of global resistance-capacitance delay, signal time-of-flight, inductance, clock and power distribution, and noise are studied. Results indicate that, while global clock frequencies will necessarily he lower than local clock speeds, NTRS expectations should be attainable to the 50 nm technology generation. Achieving these high clock speeds (10 GHz local clock) will be aided by the use of a newly proposed routing hierarchy which limits interconnect effects at each level of a design (local, isochronous, and global).

Status and review of two-dimensional carrier and dopant profiling using scanning probe microscopy

An overview of the existing two-dimensional carrier profiling tools using scanning probe microscopy includes several scanning tunneling microscopy modes, scanning capacitance microscopy, Kelvin probe microscopy, scanning spreading resistance microscopy, and dopant selective etching. The techniques are discussed and compared in terms of the sensitivity or concentration range which can be covered, the quantification possibility, and the final resolution, which is influenced by the intrinsic imaging resolution as well as by the response of the investigated property to concentration gradients and the sampling volume. From this comparison it is clear that, at present, none of the techniques fulfills all the requirements formulated by the 1997 Semiconductor Industry Association roadmap for semiconductors [National Technology Roadmap for Semiconductors (Semiconductor Industry Association, San Jose, CA, 1997)]. Most methods are limited to pn-junction delineation or provide a semiquantitative image of the differently doped regions. However, recent comparisons have shown that the techniques can provide useful information, which is not accessible with any other method.

The application of rapid thermal processing technology to the manufacture of integrated circuits—An overview

Like many of the technologies used to process integrated circuits, the road to manufacturing for rapid thermal processing (RTP) has been twisted. What began as a speculative laboratory apparatus has evolved into a cornerstone of IC technology. Qualities that make RTP desirable for IC manufacture include the ability to process wafers individually, the ability to minimize the time wafers spend at elevated temperature, the convenience of clustering RTP to other systems, and the possibility of maintaining cold reactor walls. This paper will review how these properties make RTP desirable. The paper also will present an overview of the difficulties surrounding the use of RTP and describe how many serious hurdles have been overcome. It will summarize the evolution of RTP from a curiosity to a mainstay technology in building integrated circuits. It then will describe SEMATECH’s role in working with RTP, ending with a direction for future application of RTP based on the National Technology Roadmap for Semiconductors (NTRS).

Using historical wafermap data for automated yield analysis

To be productive and profitable in a modern semiconductor fabrication environment, large amounts of manufacturing data must be collected, analyzed, and maintained. This includes data collected from in- and off-line wafer inspection systems and from the process equipment itself. This data is increasingly being used to design new processes, control and maintain tools, and to provide the information needed for rapid yield learning and prediction. Because of increasing device complexity, the amount of data being generated is outstripping the yield engineer’s ability to effectively monitor and correct unexpected trends and excursions. The 1997 SIA National Technology Roadmap for Semiconductors highlights a need to address these issues through “automated data reduction algorithms to source defects from multiple data sources and to reduce defect sourcing time.” SEMATECH and the Oak Ridge National Laboratory have been developing new strategies and technologies for providing the yield engineer with higher levels of assisted data reduction for the purpose of automated yield analysis. In this article, we will discuss the current state of the art and trends in yield management automation.

Advanced silicon IC interconnect technology and design: present trends and RF wireless implications

Back-end-of-the-line (BEOL) trends in silicon integrated circuits (ICs) include fully planarized interconnect structures with six levels of nonlocal wiring, copper metallization for improved resistance and electromigration, dual damascene patterning for improved line definition and lower BEOL manufacturing cost, and low dielectric constant interlevel dielectrics for reduced line and coupling capacitance. Advanced IC design complexity is being alleviated by the use of intellectual property (IP) cores or macrocells, particularly for advanced application-specific ICs and system-on-a-chip (SOC) implementations. Virtual Design Environment software, developed for distributed design of advanced printed circuit board, will expand to the chip level as SOC designs incorporate IP cores and involve increasingly complex interconnect wiring design. These trends are summarized and synergistic front-end developments discussed and implications for RF wireless technologies are presented. A timetable for such technology and design trends is projected based upon the 1997 National Technology Roadmap for Semiconductors.

A physical alpha-power law MOSFET model

A new compact physics-based alpha-power law MOSFET model is introduced to enable projections of low power circuit performance for future generations of technology by linking the simple mathematical expressions of the original alpha-power law model with their physical origins. The new model, verified by HSPICE simulations and measured data, includes: 1) a subthreshold region of operation for evaluating the on/off current tradeoff that becomes a dominant low power design issue as technology scales, 2) the effects of vertical and lateral high field mobility degradation and velocity saturation, and 3) threshold voltage roll-off. Model projections for MOSFET CV/I indicate a 2X-performance opportunity compared to the National Technology Roadmap for Semiconductors (NTRS) extrapolations for the 250, 180, and 150 nm generations subject to maximum leakage current estimates of the roadmap. NTRS and model calculations converge at the 70 nm technology generation, which exhibits pronounced on/off current interdependence for low power gigascale integration.

Impact of super-steep-retrograde channel doping profiles on the performance of scaled devices

Super-steep retrograded (SSR) channels were compared to uniformly doped (UD) channels as devices are scaled down from 250 nm to the 50 nm technology node, according to the scheme targeted by the National Technology Roadmap for Semiconductors (1997). The comparison was done at the same gate length L/sub gate/ and the same off-state leakage current I/sub off/, where it was found that SSR profiles always have higher threshold voltages, poorer subthreshold swings, higher linear currents, and lower saturation currents than UD profiles. Using a simulation strategy that takes into account the impact of short-channel effects on drive current, it was found that the improved short-channel effect of retrograde profiles is not enough to translate into a higher performance over the UD channels for all technologies. Hence, if the effective gate-dielectric thickness scales linearly with technology, retrograde doping will not be useful from a performance point of view. However, if the scaling of the gate-dielectric is limited to about 2 nm, SSR profiles can give higher drive current than UD channels for the end of the roadmap devices. Thus, the suitability of SSR channels over UD channels depends on the gate-dielectric scaling strategy. Simulations using a self-consistent Schrodinger-Poisson solver were also used to show that the impact of quantum mechanical (QM) effects on the long-channel characteristics of SSR and UD MOSFET's will be similar.

Metrology of vlsi critical element sizes

Methods are surveyed for measuring the critical dimensions of VLSI components. The General Physics Institute of the Russian Academy of Sciences has developed a method that meets the requirements for metrological support up to the year 2010 as set out in the National Technology Roadmap for Semiconductors of the USA.

Taking Moore's law into the next century

The Semiconductor Research Corp. is one of the few organizations to get fierce competitors like Intel, Motorola, and IBM to the same table, let alone cooperate, and it has also wrangled money-$37 million annually-from these companies and others. With this money, it funds future research to keep the engines of semiconductor production churning. In short, the SRC is bent on taking Moore's law into the next century by coordinating "precompetitive" academic research to meet industry's needs. Together with its sister organizations-the Semiconductor Industry Association and Sematech-SRC helps chart and promote the continued progress of the semiconductor industry. Their main tool for doing so is the National Technology Roadmap for Semiconductors. Published every two years, this document outlines research areas that need attention so that the industry can maintain the pace of semiconductor production. This article discusses two of those areas-interconnects, and design and test-in depth.

Low parasitic resistance contacts for scaled ULSI devices

Analysis of the components of parasitic series resistance in ULSI devices shows that interfacial contact resistivities less than 10−7 Ω cm2 will be required for sub 100-nm ULSI devices in order to stay on the historical performance trend. With dimensional scaling, the series resistance–width product decreases because channel lengths are scaled, while it increases in contacts because the contact length is decreased. Unless the contact resistivity is also reduced, the contact resistance ultimately becomes higher than the channel resistance, and no performance advantage will be obtained by making the device smaller. The challenge in meeting the contacting requirements in the 1997 National Technology Roadmap for Semiconductors is especially difficult in light of the desire to simultaneously contact both n+ and p+ junctions with a single material and given the trend towards lower processing temperatures, in which the equilibrium dopant electrical activity is lower. Several techniques, such as dielectric capping during junction annealing, are effective in reducing contact resistivity by maximizing interfacial dopant concentrations and minimizing contact barrier heights. Higher saturated drive currents, due to lowered parasitic series resistance, are observed in deep submicron devices made using silicides as diffusion sources (SADS); this technique eliminates the interfacial dopant segregation that is associated with conventional silicidation. The use of elevated source drains (ESD) also allows the use of thicker silicides while minimizing the consumption-induced increase in contact resistivity that normally accompanies silicidation; as a result, ESD devices give higher drive currents. The recrystallization of amorphous layers has been observed to result in non-equilibrium dopant activation which can be many times the equilibrium value. Finally, the use of heterojunction contacts using Si–Ge in the context of elevated source/drain devices presents another way to achieve lower contact resistance.

Prospects For Imaging of Single Dopant Atoms in Silicon by ADF Stem

The demands of the National Technology Roadmap for Semiconductors will necessitate measurement of dopant concentrations with greater spatial resolution than now possible. Current experimental and simulation experience indicate that Annular Dark Field (ADF) imaging in a Scanning Transmission Electron Microscope (STEM) should be able to determine dopant distributions with near atomic resolution. The ADF signal is derived from electrons diffusely scattered to high angles, resulting in contrast due to atomic number (Z-contrast) and defects in the crystal lattice. Thus, heavy atoms can be imaged by their Z-contrast and small atoms by the misfit strain induced in the silicon lattice. Atomic number scattering is proportional to Zn where n is between 1.5 and 1.9 depending upon the inner detector angle of the ADF detector.

A new and improved roadmap

In December 1997 the new version of the National Technology Roadmap for Semiconductors (NTRS) was released to the public. The NTRS has a position of such importance in the electronics community that Circuits and Devices Magazine has decided to dedicate much of this issue to a behind the scenes description of the key issues associated with the roadmap. It is shown that the NTRS provides the high-level vision necessary to facilitate future advancements in semiconductor technology.

Meeting RTP Temperature Accuracy Requirements: Measurement and Calibrations at Nist

ABSTRACTAlthough radiometric temperature measurement in rapid thermal processing (RTP) tools has substantially improved in terms of repeatability and uniformity, it still remains a technical challenge. The 1999 requirements of 180 nm line width technology in the 1997 National Technology Roadmap for Semiconductors (NTRS) imply an uncertainty of ± 2 °C in temperature measurement, which will continue the challenge in temperature measurement. In this paper we will discuss the NIST absolute radiometric temperature calibration, measurements, and uncertainty analysis.

Reliability and Lifing Methodologies for Microelectronic Systems

ABSTRACTIntegration of core electronic functions is progressing at a remarkable rate. The high-end computers that we are using now may be available on a single die by the turn of the century. The effect of this, and other advances on semiconductor assembly and packaging has generated the need for integrated component-level electrical thermal, and mechanical models and simulation methods, as described in the Semiconductor Industry Association national Technology Roadmap for Semiconductors. Although corporate and university research and development in the semiconductor area is intense (there are eight major university-based packaging centers around the world, for example), design/development methodologies that consider the combined and interactive effects of mechanical, thermal and chemical conditions on the reliability and durability of integrated components have been slow to develop. However, such methodologies have been developed for applications of complex composite systems in various other technologies where the operating conditions are similar. The present paper will discuss those developments and the possibility of applying that technology to microelectronic systems.

Metal–oxide–semiconductor field-effect transistor junction requirements

The detailed requirements for shallow junctions for deep sub-micron metal–oxide–semiconductor field-effect transistors are reviewed and explained. The National Technology Roadmap for Semiconductors lists the concentration and depth requirements for the next several generations of technology, but does not provide detailed explanation of the electrical requirements that drive these physical junction characteristics. There are actually many more constraints on junction formation in an integrated complimentary metal–oxide–semiconductor flow, e.g., the effect of the junction formation on the channel region, which can include poly depletion, boron penetration, and reverse short channel effects. The guidelines presented here should be useful to researchers developing ultrashallow junction processes or measurement techniques.