Narrow Width Effect Research Articles

A 65-nm 25.1-ns 30.7-fJ Robust Subthreshold Level Shifter With Wide Conversion Range

Level shifters (LS) are crucial interface circuits for multisupply voltage designs, and it is challenging to achieve both robust and efficient level conversion from subthreshold to aforementioned threshold. In this brief, we propose two circuit techniques for a novel subthreshold LS with wide conversion range. First, we introduce a novel LS circuit with NMOS-diode-based current limiter for current contention reduction to achieve robust and efficient level conversion. Second, we explore the inverse narrow width effect to increase the drivability of the pull-down devices for delay reduction. When implemented in a commercial 65-nm MTCMOS process, the proposed LS achieves robust conversion from deep subthreshold (sub-100 mV) to nominal supply voltage (1.2 V). For the target conversion from 0.3 to 1.2 V, the proposed LS shows on average 25.1-ns propagation delay, 30.7-fJ energy efficiency, and 2.5-nW leakage power across 25 test chips.

Analysis and Modeling of the Narrow Width Effect in Gate-First HKMG nMOS Transistors

This paper analyzes and models the narrow width effect (NWE) observed in nMOS transistors fabricated using a 28-nm gate-first CMOS process. It is shown that the threshold voltage of nMOS transistors increases with decrease in channel width and this effect is enhanced at shorter gate lengths, thicker hafnium oxide (HfO2), and thicker lanthanum (La) capping layer. It is also observed that this increase in threshold voltage for narrow width transistors is influenced by the device layout. The physical mechanisms responsible for the observed anomalous behavior are identified through measurements on different test structures. An empirical model is proposed to understand and model this behavior. The accuracy of the model is verified by comparing it with the experimental data. It is finally proposed that the observed NWE could be minimized by optimizing the thickness of HfO2, La capping layer, and SiO2 interfacial layer and by using different device layouts.

An Ultra-Low Voltage Level Shifter Using Revised Wilson Current Mirror for Fast and Energy-Efficient Wide-Range Voltage Conversion from Sub-Threshold to I/O Voltage

This paper presents a novel ultra-low voltage level shifter for fast and energy-efficient wide-range voltage conversion from sub-threshold to I/O voltage. By addressing the voltage drop and non-optimal feedback control in a state-of-the-art level shifter based on Wilson current mirror, the proposed level shifter with revised Wilson current mirror significantly improves the delay and power consumption while achieving a wide voltage conversion range. It also employs mixed-Vt device and device sizing aware of inverse narrow width effect to further improve the delay and power consumption. Measurement results at 0.18 μm show that compared with the Wilson current mirror based level shifter, the proposed level shifter improves the delay, switching energy and leakage power by up to 3×, 19×, 29× respectively, when converting 0.3 V to a voltage between 0.6 V and 3.3 V. More specifically, it achieves 1.03 (or 1.15) FO4 delay, 39 (or 954) fJ/transition and 160 (or 970) pW leakage power, when converting 0.3 V to 1.8 V (or 3.3 V), which is better than several state-of-the-art level shifters for similar range voltage conversion. The measurement results also show that the proposed level shifter has good delay scalability with supply voltage scaling and low sensitivity to process and temperature variations.

Simulation Analysis of Narrow Width Effect in Nano Structured Fully Depleted SOI MOSFET

This paper is about the analysis of width effect in a narrow channel fully depleted SOI MOSFET. The effect of width variation is observed on threshold voltage of Nano structured Fully Depleted SOI MOSFET. In present analysis variation in narrow channel width and short channel length of the device reduced the threshold voltage . The channel conduction is also influence by changing the Tsi and Tox of the proposed device. The Lateral direction engineering is performed during the analysis of NSMOSFET(NanoStructured).

Subthreshold DC‐gain enhancement by exploiting small size effects of MOSFETs

A pseudo-cascode split-transistor technique is proposed for DC-gain enhancement of amplifiers in the subthreshold by exploiting the small size effects of metal–oxide semiconductor field effect transistors (MOSFETs) including the reverse short-channel effect and the inverse narrow-width effect. It requires no body-biasing and occupies a small area. A compact 114 μm2 two-stage amplifier with pseudo-cascode compensation for in-pixel amplification in vision sensors has been designed using the proposed technique. A total of 10 samples of split-transistors and amplifiers fabricated in an UMC 0.18 μm standard CMOS process were measured. More than half of the tested split-transistors show considerable DC-gain enhancement over a wide range of bias currents and nine amplifiers have increased DC gains larger than 85 dB at about 4 nA power consumption.

Suppression Techniques of Subthreshold Hump Effect for High-Voltage MOSFET

In this paper, simple but very effective techniques to suppress subthreshold hump effect for high-voltage (HV) complementary metal-oxidesemiconductor (CMOS) technology are presented. Two methods are proposed to suppress subthreshold hump effect using a simple layout modification approach. First, the uniform gate oxide method is based on the concept of an H-shaped gate layout design. Second, the gate work function control method is accomplished by local ion implantation. For our experiments, 0.18 μm 20 V class HV CMOS technology is applied for HV MOSFETs fabrication. From the measurements, both proposed methods are very effective for elimination of the inverse narrow width effect (INWE) as well as the subthreshold hump.

A Novel Method to Extract Carrier Mobility and Threshold Voltage in High-Voltage DDD MOSFETs

In this work, we apply the Hauser technique and combine a newer inversion layer charge model to extract the effective channel carrier mobility (μeff) and threshold voltage (Vth) of several high-voltage DDD MOSFETs with different dimensions in channel length and width. This paper proposes and demonstrates that our new method is a novel and efficient to extract the carrier mobility and threshold voltage in the DDD MOSFET, meanwhile, the extracted data is well consistent with UT model. And, only the extracted values by our new method and BCV method can clearly reflect the narrow-width effect which results from the so called LOCOS isolation technique. Therefore, it is clearly to see that our extraction technique can exactly reflect the device characteristics in high-voltage DDD MOSFETs.

(Invited) Implant Free SiGe-Quantum Well: From Device Concept To High-Performing pFETs

In this work, three important processing steps controlling the performance of SiGe-channel Implant Free Quantum Well pFETs are presented: the thermal budget, the source/drain SiGe stressors and the narrow width effect. In the first part, it is demonstrated that the thermal budget applied on these devices needs to remain low enough to avoid channel relaxation, especially when Si1-xGex -channel with x>0.45 is considered. Second, both raised or embedded SiGe source/drain uni-axially strain the SiGe channel which highly contributes to the final device performance. Outlook for ultra-scaled SiGe-channel IFQW pFETs is also given. Last but not least, SiGe-channel has an inherent strain booster which is the narrow width effect. The latter is fully explained through experimental and simulation data. Controlling all the three aforementioned parameters allows the demonstration of a 1.5mA/um ION at 100nA/um IOFF SiGe-pFET which is in line with the best results seen from the literature.

The impact of process-induced mechanical stress in narrow width devices and variable-taper CMOS buffer design

In this work we investigate the impact of process-induced mechanical stress in narrow width devices and its implication on circuit design. We observe that the channel stress and hence drive strength of narrow width devices significantly depend upon the width of a device. We present a model for estimating width dependent channel stress and effective drive current in strain engineered devices. Width dependent change in drive strength causes WP/WN ratio (also referred to as ‘β’) in inverters to change with inverter scaling factor ‘S’. If not accounted for, this results into a suboptimal circuit design and unaccounted change in performance. Finally, considering the narrow width effects (NWEs), we propose a model to design variable-taper CMOS buffer. In our model the taper factor from one inverter stage to the next is a variable and depends upon the location of an inverter in the buffer chain. We observe that buffer designed using our model takes less area, consumes less power and gives marginal improvement in delay also.

Narrow-Width Effect on High-Frequency Performance and RF Noise of Sub-40-nm Multifinger nMOSFETs and pMOSFETs

The impact of narrow-width effects on high-frequency performance like fT, fMAX, and RF noise parameters, such as NFmin and Rn, in sub-40-nm multifinger CMOS devices is investigated in this paper. Narrow-oxide-diffusion (OD) MOSFET with smaller finger width and larger finger number can achieve lower Rg and higher fMAX. However, these narrow-OD devices suffer fT degradation and higher NFmin, even with the advantage of lower Rg. The mechanisms responsible for the tradeoff between different parameters will be presented to provide an important guideline of multifinger MOSFET layout for RF circuit design using nanoscale CMOS technology.

An Analytical Model for Deriving the 3-D Potentials and the Front and Back Gate Threshold Voltages of a Mesa-Isolated Small Geometry Fully Depleted SOI MOSFET

For a mesa-isolated small geometry SOI MOSFET, the potentials in the silicon film, front, back, and side-wall oxide layers can be derived three- dimensionally. Using Taylor's series expansions of the trigonometric functions, the derived potentials are written in terms of the natural length that can be determined by using the derived formula. From the derived 3-D potentials, the minimum values of the front and the back surface potentials are derived and used to obtain the closed-form expressions for the front and back gate threshold voltages as functions of various device parameters and applied bias voltages. Obtained results can be found to explain the drain- induced threshold voltage roll-off and the narrow width effect of a fully depleted small geometry SOI MOSFET in a unified manner.

A 40 nm Dual-Width Standard Cell Library for Near/Sub-Threshold Operation

Near/sub-threshold operation is promising to achieve energy minimization when high performance is not required. The device sizing in sub-threshold region is different from super-threshold region due to significantly different IV characteristics and impact of parasitic effects in these two regions. We have investigated the impact of the inverse narrow width effect (INWE) on transistor drain current in the near/sub-threshold region at three different technology nodes (90 nm, 65 nm, and 40 nm) and proposed an INWE-aware sub-threshold device sizing method to mitigate the impact of INWE to reduce delay, power consumption and area. We applied the proposed device sizing method to designing an INWE-aware standard cell library and achieved up to 20% less delay, 34% less power consumption and 47% less area, compared with the sub-threshold library designed using conventional sizing method. For further optimization, we proposed a dual-width library by combining the INWE-aware library and the minimum sized library. A near-threshold baseband processor designed with the dual width library achieved a total power consumption of ~ 4 μW with 6 MHz at 0.5 V, which is 30% better than the counterpart design.

Analytical modelling of inverse narrow width effect for narrow channel STI MOSFETs

This paper presents an analytical physics-based model for the width dependence of threshold voltage of nano-scale MOSFETs considering the combined effect of gate-fringing and dopant redistribution. Shallow trench isolated MOSFETs have been considered in the 90 nm and 65 nm technology node. An analytical expression for the trench oxide parasitic capacitance is derived by taking into account the enhanced depletion depth caused due to the gate-fringing field at the trench oxide sidewalls and dopant redistribution in the channel. The short channel effects on the depletion charges have been taken care of while deriving this expression. This is then used to develop the model for a width-dependent threshold voltage shift. The developed model has been validated by comparing the results predicted from the derived model with experimental data as well as simulation data. In addition, the developed model has been compared with a similar model available in the literature. It has been demonstrated that our model predicts more correctly the inverse narrow width effect of nano-scale devices compared to the existing model.

Enhancement of Data Retention Time in DRAM through Optimization of Sidewall Oxidation Precleaning

This paper proposes a DRAM data retention time enhancement method that minimizes silicon loss and undercut at STI sidewall by reducing the SC1 (Standard Cleaning) time. SC1 time optimization debilitates the parasitic electric field in STI's top corner, which reduces an inverse narrow width effect to result in reduction of channel doping density without increasing the subthreshold leakage of cell Tr. Moreover, it minimizes the electric field in depletion area from cell junction to P-well, increasing yield or data retention time.

Narrow-Width Effects on a Body-Tied Partially Depleted SOI MOSFET

In this paper, we present the investigation of narrow-width effects (NWEs) on partially depleted (PD) silicon-on-insulator (SOI) with different gate shape topologies. Based on dc/ac measurements and TCAD simulations, it shows detailed clarifications of body-tied-induced NWEs. The overall study demonstrates relationship between gate shape topologies, body-tied shape, and electrical width of the transistor. Provided physical-based analytical models are able to capture peak <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GM</i> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GG</sub> as function of gate length, transistor width, physical gate-overlap width, and number of body tied. This results in improving the overall model accuracy of body contact and floating-body PD SOI MOSFETs.

ANALYTICAL MODELING OF OVERSHOOTING EFFECT IN SUB-100 nm CMOS INVERTERS

Modeling of CMOS inverters and consequently, CMOS gates, is a critical task for improving accuracy and speed of simulation in modern sub-100 nm digital circuits. One of the key factors that determine the operation of a CMOS structure is the influence of the input-to-output coupling capacitance, also called overshooting effect. In this paper, an analytical model for this effect is presented, that computes the time period which is necessary to eliminate the extra output charge transferred through the input-to-output capacitance at the beginning of the switching process in a CMOS inverter. In addition, the maximum or minimum output voltage (depending on the considered edge) is analytically computed. The derived model is based on analytical expressions of the CMOS inverter output voltage waveform, which include the influences of both transistor currents and the input-to-output (gate-to-drain) coupling and load capacitances. An accurate version of the alpha-power law MOSFET model is used to relate the terminal voltages to the drain current in sub-100 nm devices, with an extension for varying transistor widths. The resulting model also accounts for the influences of input voltage transition time, transistors' sizes, as well as device carrier velocity saturation and narrow-width effects. The results produced by the presented model for three sub-100 nm CMOS technologies, several input voltage transition times, capacitive loads and device sizes, show very good agreement with BSIM4 HSPICE simulations.

Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge Roughness

The threshold voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) of a nanoscale transistor is severely affected by random dopant fluctuations and line-edge roughness. The analysis of these effects usually requires atomistic simulations which are too expensive in computation for statistical design. In this work, we develop an efficient SPICE simulation method and statistical variation model that accurately predict threshold variation as a function of dopant fluctuations and gate length change caused by lithography and the etching process. By understanding the physical principles of atomistic simulations, we: 1) identify the appropriate method to divide a nonuniform gate into slices in order to map those fluctuations into the device model; 2) extract the variation of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> from the strong-inversion region instead of the leakage current, benefiting from the linearity of the saturation current with respect to <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ; 3) propose a compact model of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> variation that is scalable with gate size and the amount of dopant and gate length fluctuations; and 4) investigate the interaction with non-rectangular gate (NRG) and reverse narrow width effect (RNWE). The proposed SPICE simulation method is validated with atomistic simulation results. Given the post-lithography gate geometry, this approach correctly models the variation of device output current in all operating regions. Based on the new results, we further project the amount of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> variation at advanced technology nodes, helping shed light on the challenges of future robust circuit design.

Preference of designing CMOS subthreshold logic circuits using uniform-size transistors

We demonstrate that designing subthreshold digital circuits using only similarly-sized PMOS and similarly-sized NMOS transistors usually results in faster circuits than those scaled according to conventional design methods such as Logical Effort. This statement is valid if both transistor types exhibit the inverse narrow-width effect. For proving the claim, a number of circuits are designed in both ways, compared, and the results are reported.

STI Liner Evolution as the CMOS Scaling Down

As the planar CMOS transistor devices scaling down, a lot of original process have to be optimized, developed or changed to meet the evolutional requirement, and the new process elements were continuously implemented into the manufacture. The STI-liner is one of the processes from the STI module, which comes after the trench etch and before the trench gap-fill, to provide an excellent interface and good adhesion between the silicon and the oxide. While the device scaling down, some device issues, such as, the incident of dislocations which impacted on the device leakage current, the dopant segregation which result in the threshold voltage variation and impact the inverse narrow width effect (INWE) and the gate oxide integrity (GOI), etc, are associated with the STI module and can be improved by the STI-liner process. The STI liner process is evolved from the furnace oxidation, the dry RTO, the nitrided oxide liner to the ISSG.

Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation

For nanoscale CMOS devices, gate roughness has severe impact on the device <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> characteristics, particularly in the subthreshold region. In particular, the nonrectangular gate (NRG) geometries are caused by subwavelength lithography and have relatively low spatial frequency. In this paper, we present an analytical approach to model NRG effects on <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> characteristics. To predict the change of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> characteristics due to the NRG effect, the proposed model converts the postlithography gate profile into an equivalent gate length ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Le</i> ) , which is a function of the gate bias voltage but independent of the drain bias voltage. We demonstrate the accuracy of this approach by comparing it to TCAD simulation results for 65-nm technology. The new <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Le</i> model is readily integrated into standard transistor models in traditional circuit simulation tools, such as SPICE, for both dc and transient analyses. We further develop a generic procedure to systematically extract the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Le</i> value from the postlithography gate profile. The interaction with the narrow-width effect is also efficiently incorporated into the proposed algorithm. TCAD verification demonstrates that the proposed <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Le</i> model is simple for implementation, scalable with both transistor geometries and bias conditions, and also continuous across all the operation regions.