Narrow Loop Bandwidth Research Articles

CMOS Fractional-N Frequency Synthesizer for UHF RFID Reader Applications With Transformer-Based ISF Manipulation VCO

This brief presents the CMOS fractional-N frequency synthesizer for UHF RFID reader applications. With stringent phase noise (PN) specifications for UHF RFID transceiver, our proposed synthesizer is designed to have a narrow loop bandwidth and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2^{nd}$ </tex-math></inline-formula> -order loop filter as the optimum solution paired with low noise VCO. Then, we propose the transformer-based impulse sensitivity function (ISF) manipulating VCO that supports the target PN of the frequency synthesizer, albeit with large pass-band characteristic. Compared to conventional ISF manipulating VCO, our proposed solution improves the PN by 11.3 and 14.7 dB at 10 kHz and 1 MHz offset frequencies, respectively. Figure of merit (FOM) is also superior to conventional one by 7.4 and 10.9 dB at aforementioned offset frequencies. The frequency synthesizer is implemented in a 55nm CMOS technology as a part of the UHF RFID transmitter and consumes 38.4 mW power with 0.413 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$mm^{2}$ </tex-math></inline-formula> active area. With comparison to the state-of-the-art frequency synthesizer at sub-6GHz operating frequency, only our solution satisfies the target PN for EPC global standard and various local regulations across the entire UHF RFID operating frequency range.

QPSK Demodulator Based on Wideband Acquisition System

The paper describes the design of the QPSK demodulator based satellite base station. The most important requirement of the design process is to have wide band acquisition range of 100 kHz under narrow Phase Lock Loop (PLL) bandwidth and low input Signal to Noise Ratio (SNR). The efficiency of the technique is verified with extensive simulations in MATLAB.

Design and Performance Evaluation of a Dual Antenna Joint Carrier Tracking Loop.

In order to track the carrier phases of Global Navigation Satellite Systems (GNSS) signals in signal degraded environments, a dual antenna joint carrier tracking loop is proposed and evaluated. This proposed tracking loop processes inputs from two antennas, namely the master antenna and the slave antenna. The master antenna captures signals in open-sky environments, while the slave antenna capture signals in degraded environments. In this architecture, a Phase Lock Loop (PLL) is adopted as a master loop to track the carrier phase of the open-sky signals. The Doppler frequency estimated by this master loop is utilized to assist weak carrier tracking in the slave loop. As both antennas experience similar signal dynamics due to satellite motion and clock frequency variations, a much narrower loop bandwidth and possibly a longer coherent integration can be adopted to track the weak signals in slave channels, by utilizing the Doppler aid from master channels. PLL tracking performance is affected by the satellite/user dynamics, clock instability, and thermal noise. In this paper, their impacts on the proposed phase tracking loop are analyzed and verified by both simulation and field data. Theoretical analysis and experimental results show that the proposed loop structure can track degraded signals (i.e., 18 dB-Hz) with a very narrow loop bandwidth (i.e., 0.5 Hz) and a TCXO clock.

A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces

A DLL featuring jitter reduction techniques for a noisy environment is described. It controls a loop response mode by monitoring the magnitude of input jitter caused by supply noise. This technique varies the probability of phase error tracking. It reduces the output jitter of the DLL due to a low effective variance of input phase error and a narrow effective loop bandwidth. The DLL is implemented in a 0.13 mum CMOS process. Under noisy environments, the output clock of 1 GHz has 4.58 ps RMS and 29 ps peak-to-peak jitter.

Burst-mode clock and data recovery in optical multiaccess networks using broad-band PLLs

Broad-band phase-locked loops (PLLs) are proposed for burst-mode clock and data recovery in optical multiaccess networks. Design parameters for a charge-pump PLL-based clock and data recovery (CDR) with fast phase acquisition are derived using a time-domain model that does not assume narrow loop bandwidth or small phase errors. Implementation in a half-rate CDR circuit confirms a clock phase acquisition time of 40 ns, or 100 bits at 2.488-Gb/s rate, and data recovery at 1.244-Gb/s rate with a bit-error rate of 1×10/sup -10/ (2/sup 14/-1 pseudorandom binary sequence with Manchester-encoding). The CDR was fabricated in complementary metal-oxide-semiconductor 0.18-μm technology in an area of 1×1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 54 mW of power from a 1.8-V supply.

Combating GNSS Interference with Advanced Inertial Integration

There are many scenarios where an integrated INS/GNSS navigation system may be required to operate in a high interference or weak signal environment. The GPS receiver may exploit the inertial aiding by operating with narrow tracking loop bandwidths in order to increase interference resistance. However, where a low grade INS is used, wider bandwidths are desirable to calibrate the INS errors effectively. This is important for GPS tracking loop aiding and sole-means inertial navigation during jamming. To obtain both effective INS calibration and jamming resistance, an adaptive tightly-coupled (ATC) INS/GPS integration architecture has been developed. The ATC technique has been assessed by simulation, showing that it provides a significant anti-jam margin over an INS/GPS with fixed tracking bandwidths selected for INS calibration. Compared to the deep (or ultra-tightly-coupled) integration techniques currently under development, ATC is a low cost anti-jam integration technique as it does not require a complete re-design of the navigation architecture. When there is too much interference for any GNSS signals to be tracked, the INS provides sole-means navigation. Thus, it is important to optimise the calibration of the INS when GNSS signals are available. To this end, the effects of estimating higher order inertial instrument errors and satellite range biases within the INS/GPS integration filter have been assessed.

Optimisation and sensitivity analysis of GPS receiver tracking loops in dynamic environments

For a GPS receiver, decreasing the receiver tracking loop bandwidth reduces the probability of loss of lock if there are no vehicle dynamics. However, reduced bandwidth increases tracking errors due to dynamics. Beyond a certain limit it causes a serious degradation in the dynamic tracking performance. Therefore, there is involvement of a tradeoff between two opposing considerations: narrow tracking loop bandwidths are desired for filtering noise due to thermal effects, but wide tracking loop bandwidths are desired to permit tracking of vehicle dynamics. Optimal tracking loop bandwidths, which yield the minimum errors in a certain dynamics environment, are first investigated. The linear Kalman filter is employed as the optimal estimator. The covariance for the arbitrary gain model is solved and applied to the sensitivity analysis for investigating error growth due to incorrect noise level estimate. Theoretical results are verified by numerical simulation, and results from both approaches are in very good agreement.

Detection of very weak transmissions from deep space

Designers of future planetary missions often reduce spacecraft transmitter power and oscillator stability requirements to decrease mission cost. Unfortunately, these reductions can make it impossible to detect weak signals from deep space using conventional demodulation techniques.The new Block V receiver being installed in the Deep Space Network (DSN) can recover suppressed carrier signals and can utilize very narrow loop bandwidths — as narrow as 0.1 Hz. However, operations at very narrow tracking loop bandwidths are quite sensitive to spacecraft oscillator stability. Low-cost oscillators planned for future missions can force the use of wide tracking loop bandwidths, leading to reduced carrier tracking performance. This reduced carrier tracking performance can, in turn, lead to a significant increase in required spacecraft transmitter power.This paper presents the theory behind coherent detection of very weak telemetry from deep space. It then briefly recounts tests characterizing Block V performance for the NEAR spacecraft in two-way coherent operations and presents recommendations for mission designers.

Frequency Detectors for PLL Acquisition in Timing and Carrier Recovery

A significant problem in phase-locked loop (PLL) timing and carrier extraction is the initial acquisition. Very narrow loop bandwidths are generally required to control phase jitter, and acquisition may depend on an extremely accurate initial VCO frequency (VCXO) or sweeping. We describe two simply implemented frequency detectors which, when added to the traditional phase detector, can effect acquisition even with very small loop bandwidths and large initial frequency offsets. The first is the quadricorrelator, previously applied to timing recovery by Bellisio, while the second is new, and called a rotational frequency detector. The latter, while limited to lower frequencies and higher signal-to-noise ratios, is suitable for many applications and can be implemented with simpler circuitry.