Nanowire Channel Research Articles

Demonstration of VGAA-TFETs using InAs/Si Heterojunction on SOI substrate

Tunnel field-effect transistors (TFETs) are expected to be used as a next-generation low-voltage switching device. The TFETs can lower the subthreshold slope (SS) below the physical limit (SS = 60 mV/dec at room temperature) in conventional MOSFETs. Here we demonstrated InAs nanowire (NW)/Si heterojunction vertical gate-all-around (VGAA) TFETs on silicon-on-insulator (SOI) (111) substrates toward vertical integrated circuit applications. The vertical InAs NW channels were grown by selective-area growth on thin SOI(111) substrates.

Geometric Variability‐Aware Thermal Characteristics Modeling of Nanoscale Silicon Gate‐All‐around Nanowire Transistor

Thermal management becomes increasingly important in silicon gate‐all‐around (GAA) field‐effect transistor (FETs) for 3 nm technology node and beyond. The channel thermal conductivity significantly differs from bulk silicon. Precise determination of thermal conductivity is crucial for device evaluation and optimization. This study investigates the thermal conductivity of silicon nanowires, examining the complex interplay between size and channel orientation. The conventional nonequilibrium molecular dynamics (NEMD) method is used with the standard Stillinger–Weber potential at the atomic scale. The results indicate that the thermal conductivity of silicon nanowires along the [100] direction increases monotonically with both length (L) and cross‐sectional side length (D). Conversely, the [110] direction exhibits nonmonotonic variation in thermal conductivity with D, due to increased acoustic–optic phonon scattering. For GAA FET devices with a silicon nanowire channel of L = 20 nm and D = 5 nm, the NEMD calculations yield thermal conductivities of 10.8 W m·K−1 for the [100] direction and 25.3 W m·K−1 for the [110] direction. Subsequently, the self‐heating effect (SHE) in silicon nanowire GAA FETs by technology computer‐aided design with the modified channel conductivity is analyzed. The results suggest that silicon nanowires with the [110] transport direction are more suitable for device design.

High Surface Area Metal Oxide Enhanced Self-Powered Microfluidic Device for Real-Time Pathological Detection

Biomarkers based sensing in the realm of disease prevention, its diagnosis, and drug development has shown its unique importance in health care. In particular, the platelet level in blood is strongly linked with the development of several kind of severe diseases like coronavirus disease 2019, diabetes, and microbial infections as well as individuals undergoing cancer diagnosis. Currently, commercial methods employed for platelet level determination in whole-blood are based on Coulter principle, flow cytometry, and image analysis. However, these technologies are intricate, time consuming, expensive, and require a trained operator as well as lack of portability. Considering these issues, we have developed a self-powered portable device for real-time platelet level monitoring, aimed towards point-of-care applications. The fabricated self-powered-microfluidic triboelectric nanogenerator (SPM-TENG) utilized test sample flow-resistance for sensing of platelet level and triboelectric voltage output as sensing signal. For the fine tuning of fabricated SPM-TENG, we compared the triboelectric voltage output from gold electrode measurement setup and terminal electrode measurement setup. In view of further improvement in stability, voltage output and to minimize the noise in sensing signals, the geometrical optimization of microfluidic channel was performed. In conclusion we have optimized the device as a terminal electrode measurement setup with copper tubes on terminals of microfluidic channel and copper oxide nanowires grown on the interior of copper tubes. These copper oxide nanowires provide a high surface area for solid-liquid contact separation and is responsible for enhanced sensing signal. The fabricated SPM-TENG has shown its great potential in platelet level sensing with plasma-based samples as well as whole-blood samples. The proposed device demonstrated its practicality towards real-time rapid sensing of platelet level and portability.

THERMOREGULATION SYSTEM FOR BIOSENSORS BASED ON FIELD-EFFECT TRANSISTORS WITH A NANOWIRE CHANNEL

In this work we present an automatic thermoregulation system for biosensors based on field-effect transistors with a nanowire channel, which provides full control on the required temperature regime in bioanalytical analises. The system elements, including field-effect transistors with a nanowire channel, temperature sensors and heaters, were fabricated on a single silicon cristal using electron beam lithography, reactive ion etching and high-vacuum deposition techniques. Unicue electronics have been developed to control and maintain temperature. The dependence of thermometer readout on heating power was measured, which is in good agreement with the results of numerical simulation. A demonstration of a thermoregulation system with PID-feedback was carried out, ensuring the establishment of a desiered temperature in the range of 30-70◦ C in 18 s in liquid. A demonstration of a thermoregulation system for detecting nucleic acids was carried out using synthetic single-stranded DNA, which is a gene fragment from the bacterium Escherichia coli. The minimal detectable response was observed for a sample with a concentration of 3 fM.

Exploration of underlap induced high-k spacer with gate stack on strain channel cylindrical nanowire FET for enriched performance

This research explores a comprehensive examination of gate underlap incorporated strained channel Cylindrical Gate All Around Nanowire FET having enriched performances above the requirement of the 2 nm technology node of IRDS 2025. The device installs a combination of strain engineering based quantum well barrier system in the channel region with high-k spacers sandwiching the device underlaps and stack high-k gate-oxide. The underlaps are prone to parasitic resistance and various short channel effects (SCEs) hence, are sandwiched by HfO2 based high-k. This SCE degradations and a strong electric field in the drain-channel region is rendered controlling the leakages. The strain based Nanosystem engineering is incorporated with Type-II heterostructure band alignment inducing quantum well barrier mechanism in the ultra-thin cylindrical channel region creating an electrostatic charge centroid leading to energy band bending and splitting among the two-fold and four-fold valleys of the strained Silicon layer. This provides stupendous electron mobility instigating high current density and electron velocity in the channel. Thereby, the device is susceptible to on-current enhancement via ballistic transport of carriers and carrier confinement via succumbing of quantum charge carriers. The device transconductance, Ion, Ioff, Ion/Ioff ratio are measured and the output performance (ID-VDS) characteristics is determined providing emphatic enrichments in contrast to the existing gate all-around FETs as well as the 2 nm technology node data of IRDS 2025. Hence, the strained channel Nanowire FET device developed here is presented here as the device of the future for various digital applications, RF applications and faster switching speed.

Thermoregulation System for Biosensors Based on Field-Effect Transistors with a Nanowire Channel

Thermoregulation System for Biosensors Based on Field-Effect Transistors with a Nanowire Channel

An Improved Dual-Gate Compact Model for Carbon Nanotube Field Effect Transistors with a Back-Gate Effect and Circuit Implementation

Compared to single-gate CNTFET, dual-gate structures have better electrostatic control over nanowire conductive channels. However, currently, there is insufficient research on the back-gate effect in a compact model of dual-gate CNTFET. This paper presents an improved dual-gate carbon nanotube field effect transistor (CNTFET) compact model. The functional relationship between the back-gate voltage (Vbg) and threshold voltage (Vth) is derived. And a voltage reference regulation mechanism is adopted so that the back-gate effect can be accurately reflected in the DC transfer characteristics. The influence of gate voltage and drain voltage on transmission probability is analyzed. Meanwhile, the drain current is optimized by modifying the mobility equation. This compact model is built based on Verilog-A hardware language and supports the Hspice simulation tool. Within the supply voltage of 2 V, the simulation results of the proposed compact model are in good agreement with the measurement results. Finally, based on the compact model, an operational amplifier is designed to verify its correctness and feasibility in analog integrated circuits. When the power supply voltage is 1.8 V, and the load capacitance is 2 pF, the gain is 11.8 dB, and the unit-gain-bandwidth (UGB) is 214 kHz, which proves the efficiency of our compact model.

Ultrasensitive Detection of PSA Using Antibodies in Crowding Polyelectrolyte Multilayers on a Silicon Nanowire Field-Effect Transistor.

Immunosensors based on field-effect transistors with nanowire channels (NWFETs) provide fast and real-time detection of a variety of biomarkers without the need for additional labels. The key feature of the developed immunosensor is the coating of silicon NWs with multilayers of polyelectrolytes (polyethylenimine (PEI) and polystyrene sulfonate (PSS)). By causing a macromolecular crowding effect, it ensures the "soft fixation" of the antibodies into the 3-D matrix of the oppositely charged layers. We investigated the interaction of prostate-specific antigen (PSA), a biomarker of prostate cancer, and antibodies adsorbed in the PEI and PSS matrix. In order to visualize the formation of immune complexes between polyelectrolyte layers using SEM and AFM techniques, we employed a second clone of antibodies labeled with gold nanoparticles. PSA was able to penetrate the matrix and concentrate close to the surface layer, which is crucial for its detection on the nanowires. Additionally, this provides the optimal orientation of the antibodies' active centers for interacting with the antigen and improves their mobility. NWFETs were fabricated from SOI material using high-resolution e-beam lithography, thin film vacuum deposition, and reactive-ion etching processes. The immunosensor was characterized by a high sensitivity to pH (71 mV/pH) and an ultra-low limit of detection (LOD) of 0.04 fg/mL for PSA. The response of the immunosensor takes less than a minute, and the measurement is carried out in real time. This approach seems promising for further investigation of its applicability for early screening of prostate cancer and POC systems.

Enhancing and confining light in hybrid plasmonic nanowire-integrated V-groove silicon waveguides

In recent years, the field of dielectric-plasmonic photonics has made remarkable strides, leading to the successful development of various technologies. The realization of sophisticated optical circuits on a single platform has become increasingly viable. Here we propose and investigate a hybrid dielectric waveguide integrated with plasmonics. This hybrid optical waveguide comprises a copper nanowire situated in close proximity to a silicon V-groove channel, separated by a nanoscale gap. This configuration is particularly advantageous, as achieving precise alignment of the nanowire within the V-groove addresses a fundamental challenge in engineering a fully functional integrated component. Additionally, a silicon nitride film coats the V-groove. Utilizing finite element analysis, we conduct numerical simulations to analyze field properties and modal propagation at a specific wavelength of 1550 nm. Our simulations reveal that meticulous optimization of the nanowire and V-groove channel’s geometrical parameters enables effective tailoring of the hybrid mode. This optimization results in strong mode coupling between the dielectric waveguide mode and the surface plasmon, leading to substantial field enhancement, confinement, and extended propagation length. These waveguides also hold promise for sensing applications, facilitating the detection of sample variations and locations due to pronounced mode characteristics. The proposed hybrid approach demonstrates potential for integration into high-level photonic circuits and on-chip optical computing systems.

Impact of Nanowire Radius and Channel Thickness with High-k Gate Dielectric in GAA-JLT

As the transistor’s size becomes smaller, degradation in the short-channel effects (SCEs) becomes more apparent. This leads to research work on multi-gate transistors such as the Fin-Field Effect Transistor (FinFET) and Gate-All-Around (GAA) transistor, where the 3D architecture have been shown to have superior performance as compared to conventional planar transistor. Transistor without junctions (JLT) which realizes a single type of doping has also been gaining popularity for biosensor applications due to its superior electrostatic performances in terms of Drain-Induced Barrier Lowering (DIBL), off-state leakage current (Ioff) and Subthreshold Slope (SS). In this work, the impact of changes in parameters such as the gate oxide material, nanowire radius and channel thickness toward the performance of a Gate-all-around JLT (GAA-JLT) have been studied using TCAD simulator. It was found that smaller nanowire radius and thicker channel produces lower DIBL, Ioff and SS, with the use of HfO2 as gate oxide materials shows better results than Si3N4. Meanwhile, the impact of parameters variations seemed to be negligible on the on-state current (Ion). The outcome of this work can be used as a basis to understand the impact of structural parameters variations towards the performance of a more complex GAA-JLT structure.

Design and performance of parallel-channel nanocryotrons in magnetic fields

We introduce a design modification to conventional geometry of the cryogenic three-terminal switch, the nanocryotron (nTron). The conventional geometry of nTrons is modified by including parallel current-carrying channels, an approach aimed at enhancing the device's performance in magnetic field environments. The common challenge in nTron technology is to maintain efficient operation under varying magnetic field conditions. Here, we show that the adaptation of parallel channel configurations leads to an enhanced gate signal sensitivity, an increase in operational gain, and a reduction in the impact of superconducting vortices on nTron operation within magnetic fields up to 1 T. Contrary to traditional designs that are constrained by their effective channel width, the parallel nanowire channels permits larger nTron cross sections, further bolstering the device's magnetic field resilience while improving electro-thermal recovery times due to reduced local inductance. This advancement in nTron design not only augments its functionality in magnetic fields but also broadens its applicability in technological environments, offering a simple design alternative to existing nTron devices.

Electric-field modulation of the charge-density-wave quantum condensate in h-BN/NbS3 quasi-2D/1D heterostructure devices

We report on the field-effect modulation of the charge-density-wave quantum condensate in the top-gated heterostructure devices implemented with quasi-one-dimensional NbS3 nanowire channels and quasi-two-dimensional h-BN gate dielectric layers. The charge-density-wave phases and collective current in quasi-1D NbS3 nanowires were verified via temperature dependence of the resistivity, non-linear current–voltage characteristics, and Shapiro steps that appeared in the device response under radio frequency excitation mixed with the DC bias. It was demonstrated that the electric field of the applied gate bias can reversibly modulate the collective current of the sliding charge-density-wave condensate. The collective current reduces with more positive bias, suggesting a surface effect on the condensate mobility. The single-particle current, at small source–drain biases, shows small-amplitude fluctuation behavior, attributed to the variations in the background potential due to the pinned or creeping charge-density-wave condensate. The knowledge of the electric-field effect on the charge density waves in quasi-1D NbS3 nanowires is useful for potential electronic applications of such quantum materials.

Nanowire-Enhanced Fully Transparent and Flexible Indium Gallium Zinc Oxide Transistors with Chitosan Hydrogel Gate Dielectric: A Pathway to Improved Synaptic Properties.

In this study, a transparent and flexible synaptic transistor was fabricated based on a random-network nanowire (NW) channel made of indium gallium zinc oxide. This device employs a biocompatible chitosan-based hydrogel as an electrolytic gate dielectric. The NW structure, with its high surface-to-volume ratio, facilitated a more effective modulation of the channel conductance induced by protonic-ion polarization. A comparative analysis of the synaptic properties of NW- and film-type devices revealed the distinctive features of the NW-type configuration. In particular, the NW-type synaptic transistors exhibited a significantly larger hysteresis window under identical gate-bias conditions. Notably, these transistors demonstrated enhanced paired-pulse facilitation properties, synaptic weight modulation, and transition from short- to long-term memory. The NW-type devices displayed gradual potentiation and depression of the channel conductance and thus achieved a broader dynamic range, improved linearity, and reduced power consumption compared with their film-type counterparts. Remarkably, the NW-type synaptic transistors exhibited impressive recognition accuracy outcomes in Modified National Institute of Standards and Technology pattern-recognition simulations. This characteristic enhances the efficiency of practical artificial intelligence (AI) processes. Consequently, the proposed NW-type synaptic transistor is expected to emerge as a superior candidate for use in high-efficiency artificial neural network systems, thus making it a promising technology for next-generation AI semiconductor applications.

Fabrication and performance of highly stacked GeSi nanowire field effect transistors

AbstractHorizontal gate-all-around field effect transistors (GAAFETs) are used to replace FinFETs due to their good electrostatics and short channel control. Highly stacked nanowire channels are widely believed to enhance drive current of these devices and improve overall transistor density due to their small footprint. Here we demonstrate the fabrication and characterization of nanowire FETs with stacked 16 Ge0.95Si0.05 nanowires and stacked 12 Ge0.95Si0.05 nanowires without parasitic channels. The device has the high on current (ION) of 190 μA per stack (9400 μA/μm per channel footprint) at overdrive voltage (VOV) = drain-source voltage (VDS) = 0.5 V and the high maximum transconductance (Gm,max) of 490μS (24000μS/μm) at VDS = 0.5 V among reported Si/Ge/GeSi 3D nFETs. Note that the transistor performance can be evaluated by the delay, which is depicted as CV/I. If the transistor ION is improved, the delay of standard cell can be reduced, leading to faster operation of the circuit. The subthreshold slope reduction and ION/IOFF improvement are achieved by the parasitic channel removal. In technology computer aided design (TCAD) simulation, the wrap around contacts are useful to reduce the current difference between the channels. With the proper design of transistor height, the gate delay can be also improved.

Modulation Doping of Silicon Nanowires to Tune the Contact Properties of Nano‐Scale Schottky Barriers

AbstractDoping silicon on the nanoscale by the intentional introduction of impurities into the intrinsic semiconductor suffers from effects such as dopant deactivation, random dopant fluctuations, out‐diffusion, and mobility degradation. This paper presents the first experimental proof that doping of silicon nanowires can also be achieved via the purposeful addition of aluminium‐induced acceptor states to the SiO2 shell around a silicon nanowire channel. It is shown that modulation doping lowers the overall resistance of silicon nanowires with nickel silicide Schottky contacts by up to six orders of magnitude. The effect is consistently observed for various channel geometries and systematically studied as a function of Al2O3 content during fabrication. The transfer length method is used to separate the effects on the channel conductivity from that on the barriers. A silicon resistivity is achieved as low as 0.04–0.06 Ω ·cm in the nominal undoped material. In addition, the specific contact resistivity is also strongly influenced by the modulation doping and reduced down to 3.5E‐7 Ω · cm2, which relates to lowering the effective Schottky barrier to 0.09 eV. This alternative doping method has the potential to overcome the issues associated with doping and contact formation on the nanoscale.

Enhanced Synaptic Behaviors in Chitosan Electrolyte-Based Electric-Double-Layer Transistors with Poly-Si Nanowire Channel Structures.

In this study, we enhance the synaptic behavior of artificial synaptic transistors by utilizing nanowire (NW)-type polysilicon channel structures. The high surface-to-volume ratio of the NW channels enables efficient modulation of the channel conductance, which is interpreted as the synaptic weight. As a result, NW-type synaptic transistors exhibit a larger hysteresis window compared to film-type synaptic transistors, even within the same gate voltage sweeping range. Moreover, NW-type synaptic transistors demonstrate superior short-term facilitation and long-term memory transition compared with film-type ones, as evidenced by the measured paired-pulse facilitation and excitatory post-synaptic current characteristics at varying frequencies and pulse numbers. Additionally, we observed gradual potentiation/depression characteristics, making these artificial synapses applicable to artificial neural networks. Furthermore, the NW-type synaptic transistors exhibit improved Modified National Institute of Standards and Technology pattern recognition rate of 91.2%. In conclusion, NW structure channels are expected to be a promising technology for next-generation artificial intelligence (AI) semiconductors, and the integration of NW structure channels has significant potential to advance AI semiconductor technology.

Comparative analysis of gate-oxide engineering in charge plasma based nanowire transistor

In this work, a hetero-gate-oxide charge plasma-based nanowire transistor (HGO-CPNWT) has been proposed, characterized, and a comparative analysis with the conventional charge plasma-based nanowire transistor (CCPNWT) and the Stack-Gate-Oxide CPNWT (SGO-CPNWT) has been investigated. The effects of stacking a high-κ gate oxide with a low-κ gate oxide beneath the gate and segmenting the gate oxide with a high-κ oxide at the source side and low-κ oxide at the drain side have been analyzed with the short channel effects (SCEs) parameters and radio-frequency (RF)/analog figure of merits. The HGO-CPNWT demonstrates enhanced performances in terms of Ion/Ioff of 1.66 × 108, subthreshold slope (SS) of 65.74 mV/decade, drain induced barrier lowering (DIBL) of 47.857 mV/V, peak transconductance (g m ) of 3.43 × 10−5 S/μm, and peak cut-off frequency (f t ) of 114 GHz. The simulation employs a comprehensive quantum transport model, and the comparative impacts of adjusting channel length (L g ), nanowire radius (r), and gate oxide thickness (Tox) are studied.

Transport Characteristics of Silicon Multi-Quantum-Dot Transistor Analyzed by Means of Experimental Parametrization Based on Single-Hole Tunneling Model.

The transport characteristics of a gate-all-around Si multiple-quantum-dot (QD) transistor were studied by means of experimental parametrization using theoretical models. The device was fabricated by using the e-beam lithographically patterned Si nanowire channel, in which the ultrasmall QDs were self-created along the Si nanowire due to its volumetric undulation. Owing to the large quantum-level spacings of the self-formed ultrasmall QDs, the device clearly exhibited both Coulomb blockade oscillation (CBO) and negative differential conductance (NDC) characteristics at room temperature. Furthermore, it was also observed that both CBO and NDC could evolve along the extended blockade region within wide gate and drain bias voltage ranges. By analyzing the experimental device parameters using the simple theoretical single-hole-tunneling models, the fabricated QD transistor was confirmed as comprising the double-dot system. Consequently, based on the analytical energy-band diagram, we found that the formation of ultrasmall QDs with imbalanced energetic natures (i.e., imbalanced quantum energy states and their imbalanced capacitive-coupling strengths between the two dots) could lead to effective CBO/NDC evolution in wide bias voltage ranges.

Nanoscale biosensor with integratedthermoregulation controller for DNA diagnostics.

We present a CMOS compatible technique for fabrication a sensor system based on field-effect transistors with a nanowire channel with an integrated thermoregulation elements. The proposed system provides the necessary temperature regimes for many bioanalytical studies. Field-effect transistors with a nanowire channel were fabricated using of reactive-ion etching of the upper layer of a silicon on insulator through a mask formed by electron beam lithography. Titanium thermoresistive strips for temperature control were located on the surface of the chip nearby to the nanowire transistors. Their fabrication is carried out simultaneously with the formation of contact pads to the transistor electrodes, which made it possible to avoid additional technological steps. A demonstration of a system with a built-in temperature controller for the determination of nucleic acids was carried out on model oligonucleotides. Increasing the operating temperature of the device to the ranges at which DNA hybridization occurs most efficiently allows increasing specificity and avoiding false positive results, as well as reducing analysis time. The possibility of heating up to 85–90∘C allows you to reuse such devices.

Orthogonal‐Stacking Integration of Highly Conductive Silicide Nanowire Network as Flexible and Transparent Thin Films

AbstractFlexible and transparent conductive (FTC) thin films are indispensable elements in building high‐performance flexible or soft electronics and displays. Slim inorganic nanowires (NWs), with excellent conductivity and durability, are ideal one‐dimensional ingredients to weave a quasi‐continuous FTC network. However, a precise spatial arrangement of these ultrathin NWs, to form an optimal interconnected network, represents still a difficult challenge. In this work, a catalytic growth of orderly SiNW arrays, via an in‐plane solid‐liquid‐solid mechanism, and an orthogonal‐stacking integration of the SiNWs into a 2‐layer cross‐linked network, followed by a direct alloy formation and soldering of highly conductive SiNi alloy NWs upon a flexible polyimide polymer, is demonstrated. It is also shown that the flexibility of the SiNi FTC network can be significantly enhanced with an elastic spring design of the silicide NW channels, leading to an impressive transmittance of ≈90%, a moderately equivalent sheet resistance of 130 Ω sq−1 and a durable flexibility that can sustain repetitive bending to a 2 mm radius for >1000 cycles. These results highlight the unique capabilities of an optimal spatial arrangement, precise assembly/soldering and elastic geometry design of alloy NWs to enable a new generation of high‐performance FTC thin film material for future flexible electronics, displays, and bio‐interfaced sensors.