Nanocrystal Nonvolatile Memory Devices Research Articles

Scaling dependence of memory windows and different carrier charging behaviors in Si nanocrystal nonvolatile memory devices* *Project supported by the State Key Development Program for Basic Research of China (Grant No. 2010CB934402) and the National Natural Science Foundation of China (Grant Nos. 11374153, 61571221, and 61071008).

Based on the charge storage mode, it is important to investigate the scaling dependence of memory performance in silicon nanocrystal (Si-NC) nonvolatile memory (NVM) devices for its scaling down limit. In this work, we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor (CMOS) technology. It is found that the memory windows of eight kinds of test key cells are almost the same of about 1.64 V @ ± 7 V/1 ms, which are independent of the gate area, but mainly determined by the average size (12 nm) and areal density (1.8 × 1011/cm2) of Si-NCs. The program/erase (P/E) speed characteristics are almost independent of gate widths and lengths. However, the erase speed is faster than the program speed of test key cells, which is due to the different charging behaviors between electrons and holes during the operation processes. Furthermore, the data retention characteristic is also independent of the gate area. Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration.

Applications of Focus Ion Beam Technique in the Characterization of Nanocrystal Nonvolatile Memory Devices

Extended abstract of a paper presented at Microscopy and Microanalysis 2013 in Indianapolis, Indiana, USA, August 4 – August 8, 2013.

Low operation voltage and high thermal stability of a WSi2 nanocrystal memory device using an Al2O3/HfO2/Al2O3 tunnel layer

A WSi2 nanocrystal nonvolatile memory device was fabricated with an Al2O3/HfO2/Al2O3 (AHA) tunnel layer and its electrical characteristics were evaluated at 25, 50, 70, 100, and 125 °C. The program/erase (P/E) speed at 125 °C was approximately 500 μs under threshold voltage shifts of 1 V during voltage sweeping of 8 V/−8 V. When the applied pulse voltage was ±9 V for 1 s for the P/E conditions, the memory window at 125 °C was approximately 1.25 V after 105 s. The activation energies for the charge losses of 5%, 10%, 15%, 20%, 25%, 30%, and 35% were approximately 0.05, 0.11, 0.17, 0.21, 0.23, 0.23, and 0.23 eV, respectively. The charge loss mechanisms were direct tunneling and Pool-Frenkel emission between the WSi2 nanocrystals and the AHA barrier engineered tunneling layer. The WSi2 nanocrystal memory device with multi-stacked high-K tunnel layers showed strong potential for applications in nonvolatile memory devices.

Thermal Stability of Metal-Silicide Nanocrystal Nonvolatile Memory with Barrier Engineered Tunnel Layers

WSi2 nanocrystal nonvolatile memory devices were fabricated with a silicon oxide-nitride-oxide (SiO2: 2 nm/Si3N4:2 nm/SiO2:3 nm) tunnel layer. WSi2 nanocrystals of 2.5 nm diameters and a density of 3.6 x 10(12) cm(-2) were formed using radio frequency magnetron sputtering and annealing processes. The WSi2 nanocrystal nonvolatile memory device exhibited strong thermal stability during writing/erasing operations at temperatures up to 125 degrees C. When the writing/erasing voltages were applied at +10 V/-10 V for 500 ms, the memory window of the initial approximately 2.6 V decreased by approximately 1.1 V at 25 degrees C and 0.4 V at 125 degrees C after 10(4) sec, respectively. These results show that WSi2 nanocrystals with barrier-engineered tunnel layers are possible for application in nonvolatile memory devices.

Electrical Characteristics of TiSi2 Nanocrystal Nonvolatile Memory with Barrier-Engineered Tunnel Layer

In this study, we fabricated TiSi2 nanocrystal nonvolatile memory devices with silicon nitride–oxide–nitride (NON) and SiO2 tunnel barriers. The TiSi2 nanocrystals with diameters of 2–5 nm and a density of 1.5 ×1012 cm-2 were formed using radio frequency magnetron sputtering in argon and a postannealing process. The memory effect of the TiSi2 nanocrystal memory device with the NON tunnel barrier was observed at about 0.7 V at 100 ms when the applied program/erase voltages were +7 V/-7 V. Also, the memory window of the NON tunnel barrier device was maintained up to 1.3 V after 103 s. These results indicate that the NON tunnel barrier provides an effective tunneling thickness for the fast program/erase speeds and an adequate physical thickness for long charge retention characteristics in nonvolatile memory devices.

Tungsten nanocrystal memory devices improved by supercritical fluid treatment

A supercritical CO2 (SCCO2) fluid technique is proposed to improve electrical characteristics for W nanocrystal nonvolatile memory devices, since the thickness and quality of tunnel oxide are critical issues for the fabrication of nonvolatile memory devices. After SCCO2 treatments, C-V curves are restored to normal, as well as the leakage current of W nanocrystal memory devices are reduced significantly. It reveals that W nanocrystal memory devices could be formed with shorter oxidation time, moreover, dangling bonds and trapping states initially created within an incomplete oxidized film will be efficiently repaired after SCCO2 treatment.

Growth kinetics and related physical/electrical properties of Ge quantum dots formed by thermal oxidationof Si1−xGex-on-insulator

SiGe-on-insulator (SGOI) structures were thermally oxidized to form Ge quantum dots (QDs) that areembedded in a SiO2 matrix, to systematically investigate possible structural factors that affect the properties ofGe QDs, such as size, density and even position. The properties of Ge QDs depend stronglyon the layer thickness and the geometric pattern of SGOI structures, as well as on thethermal oxidation conditions and the Ge content of the SiGe alloy. Tiny dense(3 nm/2.8 × 1012 cm−2) Ge QDs are formedby oxidizing a Si0.95Ge0.05/Si-on-insulator ‘plane’ at 900 °C, which is highly promising for nanocrystal nonvolatile memory device applications. A single Ge QD(∼10 nm) forms and is self-aligned with electrodes viaSiO2 when a SGOI nanowire with a length of less than 150 nm is thermally oxidized. This meetsthe stringent criteria for a successful single-electron device. The growth kinetics of Ge QDsformed by the oxidation of SGOI planes and nanowires is discussed. Cathodoluminescencespectra were employed to investigate the origins of photoemission from the GeQDs/SiO2 system. Ge QD resonant tunnelling diodes are also fabricated to elucidate the transport ofelectrons through such a system.

Performance of Silicon Nanocrystal Non-Volatile Memory Devices Under Various Programming Mechanisms

Non-volatile memory devices based on silicon nanocrystal synthesized with very low energy Si+ implantation are fabricated. Memory performance under various programming mechanisms including Fowler-Nordheim (FN), drain-bias channel-hot-electron (DCHE), and source-bias channel-hot-electron (SCHE) has been investigated. It is observed that the DCHE yields the largest memory window among the three programming mechanisms. The DCHE and SCHE have similar endurance characteristics, but the SCHE has a longer retention time than the DCHE. Both the DCHE and SCHE have a larger memory window, a better endurance and a longer retention time as compared to the FN. Explanations to the phenomena are given.

Synthesis and characterization of aerosol silicon nanocrystal nonvolatile floating-gate memory devices

This letter describes the fabrication and structural and electrical characterization of an aerosol-nanocrystal-based floating-gate field-effect-transistor nonvolatile memory. Aerosol nanocrystal nonvolatile memory devices demonstrate program/erase characteristics comparable to conventional stacked-gate nonvolatile memory devices. Aerosol nanocrystal devices with 0.2 μm channel lengths exhibit large threshold voltage shifts (>3 V), submicrosecond program times, millisecond erase times, excellent endurance (>105 program/erase cycles), and long-term nonvolatility (>106 s) despite thin tunnel oxides (55–60 Å). In addition, a simple aerosol fabrication and deposition process makes the aerosol nanocrystal memory device an attractive candidate for low-cost nonvolatile memory applications.

A novel, nanocrystal (nc) based non-volatile memory device

AbstractThis paper describes the fabrication, and structural and electrical characterization of a new, aerosol-nanocrystal floating-gate FET, aimed at non-volatile memory (NVM) applications. This aerosol- nanocrystal NVM device features program/erase characteristics comparable to conventional stacked gate NVM devices, excellent endurance (>105 P/E cycles), and long-term non-volatility in spite of a thin bottom oxide (55-60Å). In addition, a very simple fabrication process makes this aerosol-nanocrystal NVM device a potential candidate for low cost NVM applications.