Nanocrystal Floating Gate Memory Research Articles

Orthogonal printing of uniform nanocomposite monolayer and oriented organic semiconductor crystals for high-performance nano-crystal floating gate memory

Inkjet printing is of great interest in the preparation of optoelectronic and microelectronic devices due to its low cost, low process temperature, versatile material compatibility, and ability to precisely manufacture multi-layer devices on demand. However, interlayer solvent erosion is a typical problem that limits the printing of organic semiconductor devices with multi-layer structures. In this study, we proposed a solution to address this erosion problem by designing polystyrene-block-poly(4-vinyl pyridine)-grafted Au nanoparticles (Au@PS-b-P4VP NPs). With a colloidal ink containing the Au@PS-b-P4VP NPs, we obtained a uniform monolayer of Au nano-crystal floating gates (NCFGs) embedded in the PS-b-P4VP tunneling dielectric (TD) layer using direct-ink-writing (DIW). Significantly, PS-b-P4VP has high erosion resistance against the semiconductor ink solvent, which enables multi-layer printing. An active layer of semiconductor crystals with high crystallinity and well-orientation was obtained by DIW. Moreover, we developed a strategy to improve the quality of the TD/semiconductor interface by introducing a polystyrene intermediate layer. We show that the NCFG memory devices exhibit a low threshold voltage (<3 V), large memory window (66 V), stable endurance (>100 cycles), and long-term retention (>10 years). This study provides universal guidance for printing functional coatings and multi-layer devices.

TCAD Simulation of Nano-Crystal Floating Gate EEPROM

The present invention relates to a Nano crystal floating gate memory which is reflected as a future nonvolatile memory. The reason behind this reflection is its invulnerability in tunnel oxide to weak-point leakage and therefore its higher scalability of tunnel oxide thickness and utilization of power. The Foremost feature attribute in NCM is that it functions on a low value of voltage.

Floating Gate Memory-based Monolayer MoS2Transistor with Metal Nanocrystals Embedded in the Gate Dielectrics

Charge trapping layers are formed from different metallic nanocrystals in MoS2 -based nanocrystal floating gate memory cells in a process compatible with existing fabrication technologies. The memory cells with Au nanocrystals exhibit impressive performance with a large memory window of 10 V, a high program/erase ratio of approximately 10(5) and a long retention time of 10 years.

Flexible and transparent nanocrystal floating gate memory devices using silk protein

The charge storage behavior of a floating gate memory device using carbon nanotube-CdS nanostructures embedded in Bombyx mori silk protein matrix has been demonstrated. The capacitance – voltage characteristics in ITO/CNT–CdS-silk composite/Al device exhibits a clockwise hysteresis behavior due to the injection and storage of holes in the quantized valence band energy levels of CdS nanocrystals. The enhanced charge injection resulting in increase in memory window is observed at higher sweeping voltages. Nearly frequency independent hysteresis width over a wide range of 100kHz–2.0MHz, indicates its origin due to the charge storage in nanocrystals. The memory behavior of carbon nanotube–CdS nanostructures/silk nanocomposite devices has also been demonstrated on polyethylene terephthalate substrates, which may provide the way for flexible, transparent and printable electronic devices.

Modeling of the electrostatic coupling between nanocrystals of a disordered nanocrystal floating gate memory

This paper presents a realistic model that explicitly takes into account the electrostatic coupling between the nanocrystals of a disordered layer constituting the floating gate of a non-volatile memory. A statistical study of the neighborhood of a given nanocrystal is carried out, leading to the mean number of neighboring nanocrystals as a function of the radius of the central nanocrystal. We show that the empty neighborhood of every nanocrystal can be represented by an equivalent torus ring in the previous model of a single nanocrystal. Then the effects of charged nanocrystals are taken into account by an appropriate rigid shift of the energy levels of the central nanocrystal. The proposed model is validated by statistical comparisons with exact 3D computations, and the influence of the electrostatic coupling is analyzed and discussed.

Nanocrystal floating gate memory with solution-processed indium-zinc-tin-oxide channel and colloidal silver nanocrystals

A nanocrystal (NC) floating gate memory with solution-processed indium-zinc-tin-oxide (IZTO) channel and silver (Ag) NCs embedded in thin gate dielectric layer (SiO2(30 nm)/Al2O3(3 nm)) was fabricated. Both the IZTO channel and colloidal Ag NC layers were prepared by spin-coating and subsequent annealing, and dip-coating process, respectively. A threshold voltage shift up to ∼0.9 V, corresponding to the electron density of 6.5 × 1011 cm−2, at gate pulsing ≤10 V was achieved by the charging of high density NCs. These results present the successful non-volatile memory characteristics of an oxide-semiconductor transistor fabricated through solution processes.

Hf-based high-k materials for Si nanocrystal floating gate memories

Pure and Si-rich HfO2 layers fabricated by radio frequency sputtering were utilized as alternative tunnel oxide layers for high-k/Si-nanocrystals-SiO2/SiO2 memory structures. The effect of Si incorporation on the properties of Hf-based tunnel layer was investigated. The Si-rich SiO2 active layers were used as charge storage layers, and their properties were studied versus deposition conditions and annealing treatment. The capacitance-voltage measurements were performed to study the charge trapping characteristics of these structures. It was shown that with specific deposition conditions and annealing treatment, a large memory window of about 6.8 V is achievable at a sweeping voltage of ± 6 V, indicating the utility of these stack structures for low-operating-voltage nonvolatile memory devices.

Vertically and Laterally Self-Aligned Double-Layer of Nanocrystals in Nanopatterned Dielectric Layer for Nanocrystal Floating Gate Memory Device

The formation of vertically and laterally self-aligned double-layer of CdSe colloidal nanocrystals (NCs) in nanopatterned dielectric layer on Si substrate was demonstrated by repeating dip-coating process for NC deposition and atomic layer deposition (ALD) of Al2O3 layer. A nanopatterned-SiO2/Si substrate was formed by patterning with self-assembled diblock copolymer. After the selective deposition of the 1st NC layer inside SiO2 nanopattern by dip-coating, an Al2O3 interdielectric layer and the 2nd NC layer in Al2O3 nanopattern were sequentially deposited. The capacitance-voltage measurement of Al-gate/ALD-Al2O3(25nm)/2nd-CdSe-NCs/ALD-Al2O3(2nm)/1st-CdSe-NCs/nanopatterned-SiO2(15nm) /p-Si substrate structure showed the flatband voltage shift resulting from the charging of NCs.

Vertically and Laterally Self-Aligned Double Layers of Nanocrystals in Nanopatterned Dielectric Layer for Nanocrystal Floating Gate Memory

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Vertically and Laterally Self-Aligned Double Layer of Nanocrystals in Nanopatterned Dielectric Layer for Nanocrystal Floating Gate Memory Device

Vertically and Laterally Self-Aligned Double Layer of Nanocrystals in Nanopatterned Dielectric Layer for Nanocrystal Floating Gate Memory Device

Nonvolatile memory with Co–SiO2 core-shell nanocrystals as charge storage nodes in floating gate

In this letter, we reported nanocrystal floating gate memory with Co–SiO2 core-shell nanocrystal charge storage nodes. By using a water-in-oil microemulsion scheme, Co–SiO2 core-shell nanocrystals were synthesized and closely packed to achieve high density matrix in the floating gate without aggregation. The insulator shell also can help to increase the thermal stability of the nanocrystal metal core during the fabrication process to improve memory performance. At the request of the authors, this article is being retracted effective 1 July 2010.

Enhanced of electrical characteristics of nano-crystal floating gate memory with In2O3 nano-particles embedded in polyimide

We fabricated the nano-floating gate memory (NFGM) with In2O3 nano-particles embedded in polyimide gate insulators. Self-assembled In2O3 nano-particles were created by chemical reaction between the polymer precursor and the indium film. The particle size and density of In2O3 nano-particles were about 7 nm and 6 × 1011 cm−2, respectively. The electrical characterization of the NFGM with In2O3 nano-particles embedded in polyimide layer were measured and the memory window larger than 3.8 V was obtained from the fabricated NFGM devices due to the charging effects of In2O3 particles. Subthreshold swing, output current characteristics and retention time of fabricated NFGM devices were considerably improved by the post-annealing process in 3% hydrogen diluted H2/N2 ambient.

High-k gate oxide for silicon heterostructure MOSFET devices

Very exciting and promising results from recent developments in group-IV alloy heterostructures (viz., SiGe, SiGeC, SiC, GeC and strained-Si) have led to the belief that SiGe-based devices will open up an entirely new dimension to the future of VLSI/ULSI technology. The growth of ultrathin dielectric films on a strained group-IV alloy layer is a challenging task. As metal-oxide-semiconductor devices are being aggressively scaled down, high permittivity dielectrics are being widely investigated as alternative gate insulating layers in advanced MOS devices. The present paper reviews the recent results of different gate and high-k dielectrics on group-IV alloy layers for scaled CMOS devices, high-mobility pure-Ge channel devices and nanocrystal floating gate memories.

Enhancing memory efficiency of Si nanocrystal floating gate memories with high-κ gate oxides

High-performance floating gate memory devices of Si nanocrystal (NC) dots on HfO2 gate oxide were fabricated at temperatures below 400°C. A large counterclockwise hysteresis of 5.2V, at an applied voltage of +6V, and a stored charge density of 6×1012cm−2 were observed. Moreover, the smaller band offset of the high-κ tunneling layer resulted in higher charge tunneling probabilities towards the Si NC dots than those observed with a SiO2 tunneling layer. Advantages in terms of scaling for a high-performance and stable reliability memory device are confirmed.

Fabrication of fin field-effect transistor silicon nanocrystal floating gate memory using photochemical vapor deposition

The fin field-effect transistor (FET) silicon nanocrystal floating gate memory using the photochemical vapor deposition and the plasma doping processes was proposed. The silicon nanocrystals with a uniform size were formed on a vertical sidewall surface of the fin channel by the photochemical vapor deposition. The plasma doping was applied to form the junctions at the sidewall of the fin source-drain extension regions with a high aspect ratio. The FinFET silicon nanocrystal floating gate memory with a gate length of 100nm was successfully fabricated and it revealed a memory effect as well as a suppressed short-channel effect.

Two-dimensional arrays of ordered, highly dense and ultra-small Ge nanocrystals on thin SiO2 layers

In this work, we have developed two original processes for the fabrication of 2-dimensional arrays of ordered Ge nanocrystals embedded in thin SiO2 layers for their use in nanocrystal floating gate memories. Ordering is achieved by a combination of focused ion beam nano-patterning and self assembly of Ge islands on the patterned SiO2 surface. In the first process the Ge islands are grown by selective chemical vapor deposition of Si/Ge/Si on Si holes fabricated by FIB patterning, while the second process uses solid phase epitaxy by MBE of amorphous Ge on SiO2 at room temperature, followed by annealing for crystallization. Highly ordered and highly dense (1.5 × 1011/cm2) ultra-small (∼20 nm) Ge dots on SiO2 were achieved by both processes. This work has been carried out within the European IST project FORUM FIB: Fabrication, Organisation and Use of Memories obtained by Focused Ion Beams.

Field effect devices with metal nanoparticles integrated by Langmuir–Blodgett technique for non-volatile memory applications

In this work, we demonstrate a hybrid silicon-organic nanocrystal floating gate memory device combining organic insulating materials, metal nanoparticles and Si MOSFET. The nanocrystals were organically passivated gold nanoparticles (Au-nps) forming a monolayer which was deposited by Langmuir–Blodgett (LB) technique. The FET device is fabricated on a Silicon-on-Insulator (SOI) substrate using conventional silicon processing. The nanoparticle layer is separated from the channel area of the FET with a 5 nm thermal SiO2 film and is isolated from the Al gate contact with a LB-deposited organic insulator layer. The memory effect is tested by means of threshold voltage shift measurements under different program/erase pulses. The nanocrystals can be charged either from the channel through the thermal oxide layer or from the gate through the organic insulator depending on the pulse applied pulse characteristics.

Semiconductor Nanocrystal Floating-gate Memory Devices

ABSTRACTCurrent research directions and recent advances in the area of semiconductor nanocrystal floating-gate memory devices are herein reviewed. Particular attention is placed on the advantages, limitations and perspectives of some of the principal new alternatives suggested for improving device performance and reliability. The attractive option of generating Si nanocrystal memories by ion-beam-synthesis (IBS) is discussed with emphasis on the ultra-low-energy (ULE) regime. Pertinent issues related to the fabrication of low-voltage memory cells and the integration of the ULE-IBS technique in manufactory environment are discussed. The effect on device performance of parasitic transistors that form at the channel corner of shallow trench isolated transistors is described in details. It is shown that such parasitic transistors lead to a substantial degradation of the electrical properties of the intended devices and dominates the memory behavior of deep submicronic cells.

Characteristics of silicon nanocrystal floating gate memory using amorphous carbon/SiO2 tunnel barrier

Nanocrystal floating gate memory employing an amorphous carbon (a-C)/SiO2 double-layered tunnel barrier was fabricated. The band gap of a-C and conduction band discontinuity between a-C and Si was estimated to be 1.95 and 0.4 eV, respectively. In addition, interface states density of the a-C/SiO2/channel Si was estimated from the capacitance–voltage measurement. The nanocrystal memory using this tunnel barrier exhibited enhanced charge retention than that employing a single SiO2 tunnel barrier whereas the injection efficiency is comparable between them, which is due to the asymmetrical band profile of the tunnel barrier.

Future Silicon Nanocrystal Nonvolatile Memory Technology

AbstractA great deal of research interest is being invested in the fabrication and characterization of nanocrystal structures as charge storage memory devices. In these flash memory devices, it is possible to measure threshold voltage shifts due to charge storage of only a few electrons per nanocrystal at room temperature. Although a variety of methods exist to fabricate nanocrystals and to incorporate them into device layers, control over the critical nanocrystal dimensions, tunnel oxide thickness, and interparticle separation and isolation remains difficult to achieve. This control is vital to produce reliable and consistent devices over large wafer areas. To address these control issues, we have developed a novel two-stage ultra clean reactor in which the Si nanocrystals are generated as single crystal, nonagglomerated, spherical aerosol particles from silane decomposition at 950°C at concentrations exceeding 108 cm−3 at sizes below 10 nm. Using existing aerosol instrumentation, it is possible to control the particle size to approximately 10% on diameter. In the second reactor, particles are passivated with a high quality oxide layer with shell thickness controllable from 0.7 to 2.0 nm. The two-stage aerosol reactor is integrated to a 200 mm wafer deposition chamber such that controlled particle densities can be deposited thermophoretically. With nanocrystal deposits of 1013 cm−2, contamination of transition metals and other elements can be controlled to less than 1010 atoms cm−2.We have fabricated 0.2 μm channel length aerosol nanocrystal floating gate memory devices using conventional MOS ULSI processing on 200 mm wafers. The aerosol nanocrystal memory devices exhibit normal transistor characteristics with drive current 30 μA/μm, subthreshold slope 200 mV/dec, and drain induced barrier lowering 100 mV/V, typical values for thick gate dielectric high substrate doped nonvolatile memory devices. Uniform Fowler-Nordheim tunneling is used to program and erase these memory devices. Despite 5 nm tunnel oxides, threshold voltage shifts &gt; 2 V have been achieved with microsecond program and millisecond erase times at moderate operating voltages. The aerosol devices also exhibit excellent endurance cyclability with no window closure observed after 105 cycles. Furthermore, reasonable disturb times and long nonvolatility are obtained, illustrating the inherent advantage of discrete nanocrystal charge storage. No drain disturb was detected even at drain biases of 4V, indicating that little or no charge conduction occurs in the nanocrystal layer. We have demonstrated promise for aerosol nanocrystal memory devices. However, numerous issues exist for the future of nanocrystal devices. These technology issues and challenges will be discussed as directions for future work.