Nanocrystal Memory Research Articles

Modulating the Performance of MoS2-Based Nanocrystal Memory via Ag Ion Implantation

Nonvolatile flash memory is an important component of the semiconductor memory device, which is widely used in a variety of portable electronic equipment. As traditional flash memory approaches its physical limit, reduced reliability and performance degradation have become unavoidable. Two-dimensional (2D) layered materials exhibit excellent electronic properties even at the atomic level and have been considered as a promising development direction for future flash memory. Here, we report a MoS2-based Ag nanocrystal memory. The fabricated memory device can form the memory stack in one step through metal ion implantation, omitting tedious deposition steps compared to the conventional process. The fabricated silver nanocrystal memory exhibits a 9 V memory window and a high ON/OFF current ratio (>107). In addition, the device also exhibits good endurance characteristics of more than 104 cycles. The ion implantation technology and the 2D nature of the channel can be used for the fabrication of flexible nanoelectronic memory devices with large-scale integration.

Forming Fe nanocrystals by reduction of ferritin nanocores for metal nanocrystal memory

To fabricate metal nanocrystal (NC) memories based on iron ferritin proteins, we propose a method for embedding ferritin cores in SiO2 and performing a reduction process by rapid thermal annealing (RTA) in a hydrogen atmosphere. An iron oxide core biochemically synthesized by ferritin was used to fabricate a high-density memory node array of 7.7 × 1011 dots/cm2. Reduction intermediates and metallic iron NCs were obtained in a short time by using a hydrogen atmosphere RTA with the iron oxide core embedded in SiO2. Metal-oxide-semiconductor memory structures were fabricated, capacitance–voltage (C–V) measurements were performed, and hysteresis (memory window) suggesting charging and discharging of NCs was observed. Furthermore, the memory window and the charge injection threshold tended to vary depending on the reduction temperature. Since these values are proportional to the magnitude of the dot work function (or electron affinity), it is assumed that the formation of reduced intermediates NCs with varying work functions depending on the treatment temperature affects the electrical properties. The results suggest that the work function of the charge retention node can be controlled by reducing the metal oxide, enabling a new approach to memory design that actively employs the reduction process.

Shape-Tuned Multiphoton-Emitting InP Nanotetrapods.

As the properties of a semiconductor material depend on the fate of the excitons, manipulating exciton behavior is the primary objective of nanomaterials. Although nanocrystals exhibit unusual excitonic characteristics owing to strong spatial confinement, studying the interactions between excitons in a single nanoparticle remains challenging due to the rapidly vanishing multiexciton species. Here, a platform for exciton tailoring using a straightforward strategy of shape-tuning of single-crystalline nanocrystals is presented. Spectroscopic and theoretical studies reveal a systematic transition of exciton confinement orientation from 3D to 2D, which is solely tuned by the geometric shape of material. Such a precise shape-effect triggers a multiphoton emission in single nanotetrapods with arms longer than the exciton Bohr radius of material. In consequence, the unique interplay between the multiple quantum states allows a geometric modulation of the quantum-confined Stark effect and nanocrystal memory effect in single nanotetrapods. These results provide a useful metric in designing nanomaterials for future photonic applications.

Resistive switching memory performance in oxide hetero-nanocrystals with well-controlled interfaces

ABSTRACT For realization of new informative systems, the memristor working like synapse has drawn much attention. We developed isolated high-density Fe3O4 nanocrystals on Ge nuclei/Si with uniform and high resistive switching performance using low-temperature growth. The Fe3O4 nanocrystals on Ge nuclei had a well-controlled interface (Fe3O4/GeOx/Ge) composed of high-crystallinity Fe3O4 and high-quality GeOx layers. The nanocrystals showed uniform resistive switching characteristics (high switching probability of ~90%) and relatively high Off/On resistance ratio (~58). The high-quality interface enables electric field application to Fe3O4 and GeOx near the interface, which leads to effective positively charged oxygen vacancy movement, resulting in high-performance resistive switching. Furthermore, we successfully observed memory effect in nanocrystals with well-controlled interface. The experimental confirmation of the memory effect existence even in ultrasmall nanocrystals is significant for realizing non-volatile nanocrystal memory leading to neuromorphic devices.

Flash memory devices with metal floating gate/metal nanocrystals as the charge storage layer: A status review

Traditional flash memory devices consist of Polysilicon Control Gate (CG) - Oxide-Nitride-Oxide (ONO - Interpoly Dielectric) - Polysilicon Floating Gate (FG) - Silicon Oxide (Tunnel dielectric) - Substrate. The dielectrics have to be scaled down considerably in order to meet the escalating demand for lower write/erase voltages and higher density of cells. But as the floating gate dimensions are scaled down the charge stored in the floating gate leak out more easily via thin tunneling oxide below the floating gate which causes serious reliability issues and the whole amount of stored charge carrying information can be lost. The possible route to eliminate this problem is to use high-k based interpoly dielectric and to replace the polysilicon floating gate with a metal floating gate. At larger physical thickness, these materials have similar capacitance value hence avoiding tunneling effect. Discrete nanocrystal memory has also been proposed to solve this problem. Due to its high operation speed, excellent scalability and higher reliability it has been shown as a promising candidate for future non-volatile memory applications. This review paper focuses on the recent efforts and research activities related to the fabrication and characterization of non-volatile memory device with metal floating gate/metal nanocrystals as the charge storage layer.

Improved performance of Au nanocrystal nonvolatile memory by N2-plasma treatment on HfO2 blocking layer**Project supported by the High Level Talent Project of Xiamen University of Technology, China (Grant Nos. YKJ16012R and YKJ16016R) and the National Natural Science Foundation of China (Grant No. 51702271).

The N2-plasma treatment on a HfO2 blocking layer of Au nanocrystal nonvolatile memory without any post annealing is investigated. The electrical characteristics of the MOS capacitor with structure of Al–TaN/HfO2/SiO2/p-Si are also characterized. After N2-plasma treatment, the nitrogen atoms are incorporated into HfO2 film and may passivate the oxygen vacancy states. The surface roughness of HfO2 film can also be reduced. Those improvements of HfO2 film lead to a smaller hysteresis and lower leakage current density of the MOS capacitor. The N2-plasma is introduced into Au nanocrystal (NC) nonvolatile memory to treat the HfO2 blocking layer. For the N2-plasma treated device, it shows a better retention characteristic and is twice as large in the memory window than that for the no N2-plasma treated device. It can be concluded that the N2-plasma treatment method can be applied to future nonvolatile memory applications.

Solution-processed dual-layer Pt-SiO2 core-shell nanoparticles for nanocrystal memory with multi-bit storage states

We developed all-solution-processed dual-layer high-density Pt-SiO2 core-shell nanoparticles with ultra-thin interparticle layers within a uniform HfO2 matrix for application of nanocrystal memory. This device exhibited a clear step-like capacitance-voltage behavior at low operation voltage and four level states with a good retention property. Such a high memory performance could be attributed to the well-defined layer memory structure, high quality of the shell of nanoparticles and the interparticle layer between nanoparticle rows, appropriate nature property of Pt nanoparticles, and good material combinations of device structure. This sub-nanometer thick interparticle layer was successfully prepared through the self-assembly 3-aminopropyltrimethoxysilane (APTMS) mediated SiO2 layer, which was critical for superior multilayered device. The study result also infers Pt nanoparticles have good potential for nano-device application. We demonstrated this low-cost solution process with a low thermal budget provided a reliable approach to fabricate multilayered nanoparticle-based devices with tunable material, structure, and performance. It offers a high potential application of solution-processed nanocomposite devices for nanoparticle-based electronics.

Development of all-solution-processed nanocrystal memory

We developed an all-solution-processed nanocrystal memory containing high density (∼1 × 1012 particles·cm−2) Au-SiO2 core-shell nanoparticles (NPs) within a uniform HfO2 matrix. High-quality HfO2 high-κ oxide composed of ultra-thin (<10 nm) tunnel and control oxide layers were prepared on a silicon substrate by the spin-on sol-gel process. The Au-SiO2 core-shell nanocomposite was also constructed by solution process using 3-aminopropyltrimethoxysilane (APTMS) as a functional mediator. This APTMS provides dual functions: (1) to serve as a binder for catching colloidal Au NPs onto the HfO2 substrate, and (2) to form a protective layer to cover up the Au NP core. The APTMS shell layer was well controlled through the self-assembly monolayer (SAM) layer-by-layer process with a self-limiting feature. It thermally decomposed into sub-nano thick SiO2 shell by post-deposition annealing, playing a key role in surmounting the deficiency of HfO2 for the use of both the tunnel oxide and the control oxide in the nanocrystal memory. This approach efficiently improved the application of a crystalline HfO2 nano-film for electronic device. By elaborately integrating the solution processes of the HfO2 oxide layer and the Au-SiO2 core-shell NPs, a high-performance nanocrystal memory was obtained. This study demonstrated the potential of chemical solution process for nanofabrication application.

Influence of Pt Nanoparticle Induced Defects and Surface Coverage in Determining Asymmetric Programming/Erasing Signatures for Nanocrystal Embedded Nonvolatile Memory Applications

Metal nanocrystal embedded nonvolatile memory (NVM) devices have attracted significant attention over the past two decades as promising alternatives to conventional floating gate memory devices. This study explores the applicability of sub‐2 nm Pt nanoparticle (NP) embedded in ALD Al2O3 as charge storage nodes in Si‐based NVM devices. The influence of Pt NP‐induced border traps within Al2O3 near the Si surface and their surface coverage dependent pinning of Pt NP work function are explored as part of this study. The pinning of the nanocrystal memories induced by a high density of dangling bonds near the Pt NP/Al2O3 interface skews the expected charging/discharging characteristics with electron programming favored over holes. The degree of this pinning has been probed utilizing C–V measurements and has been dependent on the density of Al2O3 dangling bonds near the Pt NP surface. This density of dangling bonds acting as border traps has been observed as an increasing function of the Pt NP surface percent coverage. Gaining adequate understanding the location, energy, and positioning of the energy levels of these defects at the metal/high‐k interface relative to Si band gap can help overcome poor retention and leakage issues that typically compromise the performance of new generation memory devices.

Scaling dependence of memory windows and different carrier charging behaviors in Si nanocrystal nonvolatile memory devices* *Project supported by the State Key Development Program for Basic Research of China (Grant No. 2010CB934402) and the National Natural Science Foundation of China (Grant Nos. 11374153, 61571221, and 61071008).

Based on the charge storage mode, it is important to investigate the scaling dependence of memory performance in silicon nanocrystal (Si-NC) nonvolatile memory (NVM) devices for its scaling down limit. In this work, we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor (CMOS) technology. It is found that the memory windows of eight kinds of test key cells are almost the same of about 1.64 V @ ± 7 V/1 ms, which are independent of the gate area, but mainly determined by the average size (12 nm) and areal density (1.8 × 1011/cm2) of Si-NCs. The program/erase (P/E) speed characteristics are almost independent of gate widths and lengths. However, the erase speed is faster than the program speed of test key cells, which is due to the different charging behaviors between electrons and holes during the operation processes. Furthermore, the data retention characteristic is also independent of the gate area. Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration.

Carrier trapping study on a Ge nanocrystal by two-pass lift mode electrostatic force microscopy

Trapped charges inside an isolated germanium nanocrystal (Ge NC) have been studied by two-pass lift mode electrostatic force microscopy (EFM) measurements at room temperature. From visualized EFM images, electrons and holes were proven to be successfully injected and trapped in the Ge NC and distributed homogenously at the edge of its truncated spherical morphology. The Ge NC is found to have iso-potential surface and behave as a conductive material after being charged. It is also shown that the dominant charge decay mechanism during discharging of Ge NCs is related to the leakage of these trapped charges. A truncated capacitor model is used to approximate the real capacitance between the tip and Ge NC surface and to quantitatively study these trapped charges. These investigations demonstrate the potential for Ge nanocrystal memory applications.

Hierarchically built gold nanoparticle supercluster arrays as charge storage centers for enhancing the performance of flash memory devices.

Flash memory devices with high-performance levels exhibiting high charge storage capacity, good charge retention, and high write/erase speeds with lower operating voltages are widely in demand. In this direction, we demonstrate hierarchical self-assembly of gold nanoparticles based on block copolymer templates as a promising route to engineer nanoparticle assemblies with high nanoparticle densities for application in nanocrystal flash memories. The hierarchical self-assembly process allows systematic multiplication of nanoparticle densities with minimal increase in footprint, thereby increasing the charge storage density without an increase in operating voltage. The protocol involves creation of a parent template composed of gold nanoclusters that guides the self-assembly of diblock copolymer reverse micelles which in turn directs electrostatic assembly of gold nanoparticles resulting in a three-level hierarchical system. Capacitance-voltage (C-V) measurements of the hierarchical nanopatterns with a metal-insulator-semiconductor capacitor configuration reveal promising enhancement in memory window as compared to nonhierarchical nanoparticle controls. Capacitance-time (C-t) measurements show that over half the stored charges were retained when extrapolated to 10 years. The fabrication route can be readily extended to programmed density multiplication of features made of other potential charge storage materials such as platinum, palladium, or hybrid metal/metal oxides for next generation, solution-processable flash memory devices.

Memory effect by carrier trapping into V3Si nanocrystals among SiO2 layers on multi-layered graphene layer.

We report the electrical characteristics and conduction mechanism of a resistive switching memory device consisting of V3Si nanocrystals embedded in the SiO2 layer on multi-layered graphene. The V3Si nanocrystals with average size of 5 nm were formed between the SiO2 layers by thin film deposition and post-annealing process at 800 degrees C for 5 s. The current values of high (HRS) and low resistance states (LRS) at 1 V were measured to be about 3.26 x 10(-9) A and 3.11 x 10(-8) A, respectively. The ratio of the HRS and LRS after applying sweeping bias of ± 6 V appeared to be about 9.54 at 1 V. The resistance switching could originate from the effect of carrier trap and emission into the V3Si nanocrystals via the tunneling, space charge limited current, and thermionic emission mechanisms controlled by the modulation of the Fermi level of the graphene layer. The V3Si nanocrystals memory device has a strong possibility for the application of nonvolatile memory devices.

Growth of high-density Ir nanocrystals by atomic layer deposition for nonvolatile nanocrystal memory applications

A careful investigation is made of the growth of Ir nanocrystals (NCs) on Al2O3 by atomic layer deposition (ALD), and a charge trapping memory device using ALD-grown Ir NCs as the charge trapping layer and ALD-grown Al2O3/HfO2 as the tunneling/blocking layers is fabricated. It is found that the ex situ nucleation of Ir NCs on ALD-grown Al2O3 is difficult, though in situ growth can produce pure metallic Ir NCs with a face-centered cubic crystalline phase directly on ALD-grown Al2O3 at the initial growth stage, which follows the nucleation incubation model. The growth of these metallic Ir NCs is attributed to the presence of a uniform coverage of reactive groups (hydroxyl or dimethylaluminum) on the as-deposited fresh ALD-grown Al2O3 surface, which greatly promotes the uniform nucleation of Ir. Electrical measurements of p-Si/Al2O3/Ir NCs/HfO2 memory cells exhibit a large memory window of 4.2 V at the sweeping gate voltage of ±10 V, and a ∼76% retention property after 104 s at 75 °C. Also, a stable memory window of ∼2 V is achieved during the first 105 program/erase cycles under a ±10 V/10 ms program/erase operation. In situ ALD-grown Ir NCs with the highest density of 0.6 × 1012/cm2 provide a potential approach to fabricate large-area high-density NCs for future ultrahigh-density nonvolatile NC memory applications.

Oxygen plasma immersion ion implantation treatment to enhance data retention of tungsten nanocrystal nonvolatile memory

Data retention characteristics of tungsten nanocrystal (W-NC) memory devices using an oxygen plasma immersion ion implantation (PIII) treatment are investigated. With an increase of oxygen PIII bias voltage and treatment time, the capacitance–voltage hysteresis memory window is increased but the data retention characteristics become degraded. High-resolution transmission electron microscopy images show that this poor data retention is a result of plasma damage on the tunneling oxide layer, which can be prevented by lowering the bias voltage to 7 kV. In addition, by using the elevated temperature retention measurement technique, the effective charge trapping level of the WO3 film surrounding the W-NCs can be extracted. This measurement reveals that a higher oxygen PIII bias voltage and treatment time induces more shallow traps within the WO3 film, degrading the retention behavior of the W-NC memory.

Effects of charge storage dielectric thickness on hybrid gadolinium oxide nanocrystal and charge trapping nonvolatile memory

The characteristics of hybrid gadolinium oxide nanocrystal (Gd2O3-NC) and gadolinium oxide charge trapping (Gd2O3-CT) memories were investigated with different Gd2O3 film thickness. By performing the rapid thermal annealing on Gd2O3 films with different thickness, the Gd2O3-NCs with the diameter of 6–9 nm for charge storage, surrounded by the amorphous Gd2O3 (α-Gd2O3) layer, were formed. The α-Gd2O3 layer was considered to be the charge trapping layer, resulting in the large memory window of Gd2O3-NC/CT memories with thick Gd2O3 film. The charge trapping energy level of the Gd2O3-NCs and α-Gd2O3 layer was extracted to be 0.16 and 0.45 eV respectively by using the temperature-dependent retention measurement. Further, after a 106 program/erase cycling operation, the memory with thin Gd2O3 film can be predicted to sustain a 94% memory window of the first cycling one while the memory with thick Gd2O3 film suffered from a 30% charge loss because of the traps within the α-Gd2O3 layer. The Gd2O3 film thickness of 10 nm was optimized to exhibit superior performances of the Gd2O3-NC/CT memory, which can be applied into the nonvolatile memory.

High-Performance Double-Layer Nickel Nanocrystal Memory by Ion Bombardment Technique

A novel ion bombardment (IB) technique is presented to fabricate and embed double-layer (DL) Ni nanocrystal (NC) in silicon nitride for TaN/Al2O3/Si3N4/SiO2/Si nonvolatile memory applications. In contrast to other methods of forming DL metal NC, the IB technique is a relatively simple fabrication method and completely compatible with the current IC manufacturing technologies. Using the IB technique, a high-quality ultrathin interlayer between top and bottom layered NCs can be easily formed and controlled. Compared with the control sample, the IB-induced DL Ni NC memory exhibits superior performance in terms of faster program and erase (P/E) speeds, longer data retention, better endurance, negligible program disturbance, and great potential for a multilevel operation. In addition, the IB-induced DL Ni NC device also shows higher P/E efficiency as well as similar excellent reliability by comparison with other conventional DL metal NC memories due to the high-quality ultrathin interlayer.

Charge storage characteristics of Au nanocrystal memory improved by the oxygen vacancy-reduced HfO2 blocking layer

This study characterizes the charge storage characteristics of metal/HfO2/Au nanocrystals (NCs)/SiO2/Si and significantly improves memory performance and retention time by annealing the HfO2 blocking layer in O2 ambient at 400°C. Experimental evidence shows that the underlying mechanism can be effectively applied to reduce oxygen vacancy and suppress unwanted electron trap-assisted tunneling. A memory window of 1 V at an applied sweeping voltage of ±2 V is also shown. The low program/erase voltage (±2 V) and the promising retention performances indicate the potential application of NCs in low-voltage, non-volatile memory devices.

Applications of Focus Ion Beam Technique in the Characterization of Nanocrystal Nonvolatile Memory Devices

Extended abstract of a paper presented at Microscopy and Microanalysis 2013 in Indianapolis, Indiana, USA, August 4 – August 8, 2013.

Implementation of Si nanocrystals in non-volatile memory devices

Growth in the demand for flash non-volatile memory (NVM) has been driven by mass storage applications, as well as mobile and consumer electronics. Embedded flash is utilized in microcontrollers where system speed, security, and customization are important. The challenges of embedded flash memories, usable across a range of products from consumer to automotive, include the ability to store and update data over a wide range of temperature and voltage corners. Nanocrystal memory is of great interest because of its improved reliability due to the localized nature of the charge storage, as well as its process simplicity and ease of integration into the complementary metal–oxide–semiconductor (CMOS) platform. Additionally, scaling of the dielectric thickness allows for reduced operating voltages and module size. Nanocrystal deposition techniques have been developed to produce uniform, controllable films, and device performance is well-behaved. The first commercially available microcontroller family built with silicon nanocrystals as the storage medium is now in production, built on a 90 nm platform and using a split-gate architecture. In this work, device and materials issues related to silicon nanocrystal memory are reviewed, and memory array performance discussed. Finally, scalability of nanocrystal memories is considered, where excellent performance and reliability can be achieved down to the 40 nm technology node and further.