NAND Flash Memory Research Articles

Adaptive Bitline Voltage Countermeasure for Neighbor Wordline Interference in 3D NAND Flash Memory-Based Sensors.

Three-dimensional NAND flash memory is widely used in sensor systems as an advanced storage medium that ensures system stability through fast data access. However, in flash memory, as the number of cell bits increases and the process pitch keeps scaling, the data disturbance becomes more serious, especially for neighbor wordline interference (NWI), which leads to a deterioration of data storage reliability. Thus, a physical device model was constructed to investigate the NWI mechanism and evaluate critical device factors for this long-standing and intractable problem. As simulated by TCAD, the change in channel potential under read bias conditions presents good consistency with the actual NWI performance. Using this model, NWI generation can be accurately described through the combination of potential superposition and a local drain-induced barrier lowering (DIBL) effect. This suggests that a higher bitline voltage (Vbl) transmitted by the channel potential can restore the local DIBL effect, which is ever weakened by NWI. Furthermore, an adaptive Vbl countermeasure is proposed for 3D NAND memory arrays, which can significantly minimize the NWI of triple-level cells (TLC) in all state combinations. The device model and the adaptive Vbl scheme were successfully verified by TCAD and 3D NAND chip tests. This study introduces a new physical model for NWI-related problems in 3D NAND flash, while providing a feasible and promising voltage scheme as a countermeasure to optimize data reliability.

Controlling the Carrier Injection Efficiency in 3D Nanocrystalline Silicon Floating Gate Memory by Novel Design of Control Layer.

Three-dimensional NAND flash memory with high carrier injection efficiency has been of great interest to computing in memory for its stronger capability to deal with big data than that of conventional von Neumann architecture. Here, we first report the carrier injection efficiency of 3D NAND flash memory based on a nanocrystalline silicon floating gate, which can be controlled by a novel design of the control layer. The carrier injection efficiency in nanocrystalline Si can be monitored by the capacitance-voltage (C-V) hysteresis direction of an nc-Si floating-gate MOS structure. When the control layer thickness of the nanocrystalline silicon floating gate is 25 nm, the C-V hysteresis always maintains the counterclockwise direction under different step sizes of scanning bias. In contrast, the direction of the C-V hysteresis can be changed from counterclockwise to clockwise when the thickness of the control barrier is reduced to 22 nm. The clockwise direction of the C-V curve is due to the carrier injection from the top electrode into the defect state of the SiNx control layer. Our discovery illustrates that the thicker SiNx control layer can block the transfer of carriers from the top electrode to the SiNx, thereby improving the carrier injection efficiency from the Si substrate to the nc-Si layer. The relationship between the carrier injection and the C-V hysteresis direction is further revealed by using the energy band model, thus explaining the transition mechanism of the C-V hysteresis direction. Our report is conducive to optimizing the performance of 3D NAND flash memory based on an nc-Si floating gate, which will be better used in the field of in-memory computing.

Analysis of Channel Potential Recovery According to the Back Pattern in 3D NAND Flash Memory

This study analyzed the recovery of channel potential according to the program states of adjacent cells. When the verify operation ended, and all voltages dropped to 0 V and the decreased potential of the floating channel caused by the down-coupling phenomenon was recovered continuously over time, regardless of the program states of adjacent WLs. The extent of channel potential recovery showed a similar tendency to that of the variation in the electron concentration of the floating channel. The electron–hole pair recombination decreased the electron concentration, resulting in channel potential recovery. When the adjacent WLs were programmed in a low state, additional electron–hole pair recombination and hole diffusion occurred in the floating channel. Therefore, the channel potential recovered quickly when the adjacent WLs programmed in a low state compared to when they programmed in a high state.

PSA-Cache: A Page-state-aware Cache Scheme for Boosting 3D NAND Flash Performance

Garbage collection (GC) plays a pivotal role in the performance of 3D NAND flash memory, where Copyback has been widely used to accelerate valid page migration during GC. Unfortunately, copyback is constrained by the parity symmetry issue: data read from an odd/even page must be written to an odd/even page. After migrating two odd/even consecutive pages, a free page between the two migrated pages will be wasted. Such wasted pages noticeably lower free space on flash memory and cause extra GCs, thereby degrading solid-state-disk (SSD) performance. To address this problem, we propose a page-state-aware cache scheme called PSA-Cache , which prevents page waste to boost the performance of NAND Flash-based SSDs. To facilitate making write-back scheduling decisions, PSA-Cache regulates write-back priorities for cached pages according to the state of pages in victim blocks. With high write-back-priority pages written back to flash chips, PSA-Cache effectively fends off page waste by breaking odd/even consecutive pages in subsequent garbage collections. We quantitatively evaluate the performance of PSA-Cache in terms of the number of wasted pages, the number of GCs, and response time. We compare PSA-Cache with two state-of-the-art schemes, GCaR and TTflash, in addition to a baseline scheme LRU. The experimental results unveil that PSA-Cache outperforms the existing schemes. In particular, PSA-Cache curtails the number of wasted pages of GCaR and TTflash by 25.7% and 62.1%, respectively. PSA-Cache immensely cuts back the number of GC counts by up to 78.7% with an average of 49.6%. Furthermore, PSA-Cache slashes the average write response time by up to 85.4% with an average of 30.05%.

Mechanical stress in a tapered channel hole of 3D NAND flash memory

Mechanical stress impact according to the taper angle in 3D vertical NAND flash memory (V-NAND) was investigated using technology computer-aided design simulation (TCAD). In the non-tapered V-NAND, the stress of the polysilicon channel is similar regardless of the number of layers and the position of the WL. On the other hand, in tapered V-NAND, as the taper angle decreases, the CD variation of the channel hole increases, and the compressive stress increases close to the lower WL. The compressive stress applied to the polysilicon channel produces a negative threshold voltage shift (ΔVth) due to conduction band lowering. In tapered V-NAND, the lower WL has a larger ΔVth than the upper WL, and a non-uniform Vth shift occurs. However, as the gate length of the tapered V-NAND is scaled down, the stress of the polysilicon channel is decreased, and the stress difference between the lower WL and upper WL is reduced; therefore, the non-uniform Vth shift is suppressed.

Inhibited Channel Potential of 3D NAND Flash Memory String According to Transient Time

The channel potential of natural local self-boosting (NLSB) effects in 16-layer 3D NAND flash memory was analyzed according to transient time. After a program pulse was applied to the selected word line (WL) of the inhibited string channel, the channel potential of the selected WL increased owing to NLSB. The channel potential of the selected WL, increased by NLSB, was analyzed as a function of the threshold voltage (Vth) of the adjacent cell and according to the change in time. The analysis confirmed that the channel potential value decreased gradually over time. However, it was confirmed that the rate at which the channel potential decreases was different depending on the Vth of the adjacent cell. The number of electrons in nitride is different for each Vth. These electrons affect the holes of the spacer and channel. The analysis also confirmed that the movement of electrons was caused by the difference in the hole concentration in the spacer and channel.

Improvement of memory performance of 3-D NAND flash memory with retrograde channel doping

The examination of the effect of retrograde channel doping on reliability and performance of 3-D junction-free NAND based flash memory is done for this paper. Specifically, we study the program characteristics, data retention capability junction-free NAND flash memory with half pitch range from 35 nm to 12 nm. Based on our analysis, we highlight that the retrograde channel doping approach can improve not only the SCEs but also the program speed and data control time for 3-D junction-free NAND flash memory, without varying the oxide stack in charge trap-based flash memory.

Microscopic physical origin of charge traps in 3D NAND flash memories

We performed the first-principles calculations for a nitrogen vacancy (V N) and hydrogen(H) atom in β-Si3N4 to clarify the atomistic origin of charge traps in silicon nitride (SiN) layers and charge-trapping mechanism used for 3D NAND flash memories. The present calculations showed that V N attracted H impurities and the structures where one Si dangling bond on V N is terminated by an H atom and the remaining two Si atoms form Si–Si bond (V N-H complexes) were formed in SiN layers. We investigated the electronic behavior of V N-H complexes and found that V N-H complexes act as charge traps. From our results, the atomistic origin of charge traps in SiN layers seems to be V N-H complexes.

PMOS junction optimization for 3D NAND FLASH memory with CMOS under array

Continuous scaling the 3D NAND technology from CMOS Near Array (CNA) to CMOS Under Array (CUA) can achieve a minimal cell footprint and die size. However, the CMOS performance needs to overcome the short channel effect (SCE) and dopant deactivation since the thermal budget of the array cell would be fully executed on the CMOS transistor when 3D NAND architecture changes from CNA to CUA. Applying Cryogenic technology and carbon co-implantation can boost the CMOS performance by reducing implant induced defects in end of range (EOR) and controlling the interstitials to minimize dopants, such as boron or phosphorus, transient enhanced diffusion (TED) during subsequent thermal process. In this paper, using cold carbon implantation on P-type MOS S/D extension and P-type plug contact process of 96 layer 3D NAND FLASH memory with CUA structure can improve the device characteristics when decreasing the gate length and distance of the poly to contact, such as less SCE and better device On/Off performance. Besides, junction variability improvement is also demonstrated.

Exploiting Metadata to Estimate Read Reference Voltage for 3-D nand Flash Memory

In consumer electronics, 3-D NAND flash memory has become the state-of-the-art storage medium due to the multi-bit storage per cell and 3-D stacking technology. However, flash memory cells are commonly vulnerable to numerous types of circuit-level noise, resulting in threshold voltage distribution distortion and decreased reliability. Characterization of the threshold voltage distribution and modeling of optimal read reference voltages can help to mitigate the reliability deterioration. We provide a solution for improving the reliability of flash memories while reducing their implementation cost in this paper. The proposed pre-processing method is shown to yield a smaller number of scanning voltage steps reducing the time overhead and energy consumption of multiple read operations during the characterization of threshold voltage distributions. We propose a single state asynchronous estimation (SSAE) method to estimate optimal read reference voltages. Compared with the advanced two-state asynchronous estimation (TSAE) method, it is shown to reduce the computational and space overhead by half. Furthermore, compared with using the default read reference voltages, it is also shown to reduce RBER without exact knowledge of noise.

Irregular-Mapped Protograph LDPC-Coded Modulation: A Bandwidth-Efficient Solution for 6G-Enabled Mobile Networks

The huge amount of data produced in the 6G networks not only brings new challenges to the reliability and efficiency of mobile devices but also drives rapid development of new storage techniques. With the benefits of fast access speed and high reliability, NAND flash memory has become a promising storage solution for the 6G networks. In this paper, we investigate a protograph-coded bit-interleaved coded modulation with iterative detection and decoding (BICM-ID) utilizing irregular mapping (IM) in the NAND flash-memory systems. First, we propose an enhanced protograph-based extrinsic information transfer (EPEXIT) algorithm to facilitate the analysis of protograph codes in the IM-BICM-ID systems. With the use of EPEXIT algorithm, a simple design method is conceived for the construction of a family of high-rate protograph codes, called irregular-mapped accumulate-repeat-accumulate (IMARA) codes, which possess excellent decoding thresholds and linear-minimum-distance-growth property. Furthermore, motivated by the voltage-region iterative gain characteristics of IM-BICM-ID systems, a novel read-voltage optimization scheme is developed to acquire accurate read-voltage levels, thus minimizing the decoding thresholds (in dB) of protograph codes. Analyses and simulations indicate that the proposed IMARA-aided IM-BICM-ID scheme and read-voltage optimization scheme remarkably improve the convergence and decoding performance of flash-memory systems. Thus, the proposed protograph-coded IM-BICM-ID can be viewed as a reliable and efficient storage solution for the new-generation mobile networks, such as Internet of Vehicles.

Improved ISPP scheme for narrow threshold voltage distribution in 3-D NAND flash memory

Three-dimensional NAND flash technology exhibits a trend of increasing bit density. The narrow threshold voltage (Vth) distribution of each program state in a chip is important for increasing the number of bits in a multilevel cell (MLC) technique. An abnormal program cell (APC), which is an excessively programmed cell whose Vth overlaps with the next program state, increases the Vth distribution width (Wv). The wide Vth distribution makes it difficult to distinguish the data stored in each cell and causes data errors. In this study, an improved incremental step pulse programming (ISPP) method to narrow the Vth distribution has been proposed. As the programming step voltage (Vstep) decreases immediately before the target cells pass the nth program verify level (PVn), the difference between Vth and PVn decreases, causing a reduction in the number of APCs. Therefore, in the improved ISPP, the Vstep is selectively reduced at the target ISPP steps at which most cells are predicted to be programmed in the next ISPP step for each program state. As a result, the Wv of the improved scheme decreases compared to the conventional scheme with the minimum increase in the total number of program pulses. Larger bit density is feasible by applying improved ISPP, resulting in high-capacity NAND flash memory.

Quantitative analysis of irregular channel shape effects on charge-trapping efficiency using massive 3D NAND data

The randomly fluctuating trap efficiency of taper-etched nanowire thin-film transistors was investigated by measuring a very large statistical ensemble of three-dimensional NAND flash memory cells. We made trapping in n-bit multi-level cells using incremental step pulse programming and observed the widening of the threshold voltage distribution caused by abnormal program cells. Further, we classified the components that broaden the threshold voltage distribution in both chip- and wafer-level measurements to analyze behaviors of the randomly fluctuating abnormal program cell. The variations in reading and programming operations are difficult to separate because they act simultaneously in the data reading and writing operations. For each pulse of the programming, the variations occur in reading for verification, in programming itself, and in reading after program completion. To analyze the inseparable variation, we used a method to extract only the intrinsic over-programming by removing variations in the read operation from the entire abnormal program cell. Using this extraction method, we could distinguish between the simultaneous read variation and over-programming. In particular, the unpredictable effect of the three-dimensional structure, such as the irregular shape and different radius due to the tapered channel hole profile from the nonideal etching process, was calculated and verified using experimental data. We quantitatively analyzed the experimental data one by one for each cell within the entire distribution, and each pulse of dozens in the programming scheme. This analysis provides quantitative information on the variations in charge-trapping efficiency and the threshold voltage distribution width by irregular-shaped tunneling layers.

Holistic Optimization of Trap Distribution for Performance/Reliability in 3-D NAND Flash Using Machine Learning

A machine learning (ML) method was used to optimize the trap distribution of the charge trap nitride (CTN) to simultaneously improve its performance/reliability (P/R) characteristics, which are tradeoffs in 3-D NAND flash memories. Using an artificial neural network (ANN), we modeled the relationship between trap distributions and P/R characteristics. The ANN was trained using a large experimentally-calibrated technology computer-aided design (TCAD) simulation dataset. The gradient descent method was adapted to optimize the trap distribution, achieving the best P/R characteristics based on the well-trained ANN. Eventually, we found the best trap profile distributed in both space and energy. In particular, the energetic trap distribution had a larger impact on the P/R characteristics than that of the spatial trap distribution. Furthermore, in terms of the P/R characteristics, it was generally preferable to increase all inputs of the energetic trap distribution. However, the acceptor-like trap energy level ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$E_{TA}$ </tex-math></inline-formula> ) and its standard deviation ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma _{EA}$ </tex-math></inline-formula> ) caused a tradeoff between P/R characteristics; therefore, ML was used to determine their optimal points. The proposed ML method allows the optimization of trap distribution to obtain the best P/R characteristics rapidly and quantitatively. Our findings could be used as a guideline for determining the physical properties of CTN in 3-D NAND flash cells.

Intrablock Wear Leveling to Counter Layer-to-Layer Endurance Variation of 3-D NAND Flash Memory

A shift to 3-D NAND technology has resulted in flash memory blocks that include many pages, leading to “big-block” management issues in storage systems. This article experimentally explores endurance variability in 3-D NAND flash memory blocks and finds that pages in the bottom and top layers exhibit lower endurance than pages in the middle layers. We find that erase threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{t}{)}$ </tex-math></inline-formula> variation between the layers is the root cause for the observed endurance variation. This variation in endurance among pages can cause severe underutilization of flash memory. To counter these effects and improve the overall utilization of 3-D NAND flash memories, we propose an intrablock wear-leveling algorithm based on dynamic, incremental, and layer-aware downsizing of flash memory blocks.

On the Design of SSRS and RS Codes for Enhancing the Integrity of Information Storage in NAND Flash Memories

On the Design of SSRS and RS Codes for Enhancing the Integrity of Information Storage in NAND Flash Memories

Analytical Modeling of Threshold Voltage and Subthreshold Slope for 3-D NAND Flash Memory With a Non-Uniform Doping Profile

Analytical Modeling of Threshold Voltage and Subthreshold Slope for 3-D NAND Flash Memory With a Non-Uniform Doping Profile

3D NAND Flash Memory Cell Current and Interference Characteristics Improvement With Multiple Dielectric Spacer

3D NAND Flash Memory Cell Current and Interference Characteristics Improvement With Multiple Dielectric Spacer

Read Reference Voltage Adaptation for NAND Flash Memories With Neural Networks Based on Sparse Histograms

Read Reference Voltage Adaptation for NAND Flash Memories With Neural Networks Based on Sparse Histograms

Separating the File System Journal to Reduce Write Amplification of Garbage Collection on ZNS SSDs

Solid-State Drives (SSDs), despite their outstanding I/O performance, suffer from the garbage collection overhead incurred by out-place update scheme that addresses the erase-before-write constraint of NAND flash memory. The Zoned Namespace SSD (ZNS SSD) is a state-of-the-art storage technology that divides NAND flash memory space within an SSD into zones and allows the host to directly assign certain zone for a write request. Therefore, the ZNS SSD can minimize the garbage collection overhead by allocating data with similar update patterns to the same zone. However, legacy journaling file systems still cannot actively exploit the advantages of ZNS SSDs, and journal data and file data with obviously different update patterns are written together in the same zone. In this paper, we propose new file system journal placement scheme that separates journal data into a dedicated zone to minimize write amplification due to garbage collection, noting the characteristics of journal data in the Ext4 file system. The proposed scheme is implemented in Linux kernel and carefully evaluated. The evaluation results show that our scheme removes the unnecessary copying of journal data during garbage collection of ZNS SSD and reduces the valid page copies caused by garbage collection by up to 26.8%.