NAND Flash-based Storage Systems Research Articles

Energy-Efficient Partial LDPC Decoding for NAND Flash-Based Storage Systems

A new decoding method for low-density parity-check (LDPC) codes is presented to lower the energy consumption of LDPC decoders for NAND flash-based storage systems. Since the channel condition of NAND flash memory is reliable for most of its lifetime, it is inefficient to apply the maximum-effort decoding with the full parity-check matrix (H-matrix) from the beginning of the lifespan. As the energy consumption and the decoding latency are proportional to the size of the H-matrix used in decoding, the proposed algorithm starts the decoding with a partial H-matrix selected by considering the channel condition. In addition, the proposed partial decoding provides various error-correcting capabilities by adjusting the partial H-matrix. Based on the proposed partial decoding algorithm, a prototype decoder is implemented in a 65 nm CMOS process to decode a 4 KB LDPC code. The proposed decoder reduces energy consumption by 93% compared to the conventional LDPC decoding architecture at maximum.

Read latency variation aware performance optimization on high-density NAND flash based storage systems

Read latency variation aware performance optimization on high-density NAND flash based storage systems

PA-LIRS: An Adaptive Page Replacement Algorithm for NAND Flash Memory

NAND flash memory is increasingly widely used as a storage medium due to its compact size, high reliability, low-power consumption, and high I/O speed. It is important to select a powerful and intelligent page replacement algorithm for NAND flash-based storage systems. However, the features of NAND flash, such as the asymmetric I/O costs and limited erasure lifetime, are not fully taken into account by traditional strategies. In order to address these existing shortcomings, this paper suggests a new page replacement algorithm, called probability-based adjustable algorithm onlow inter-reference recency set (PA-LIRS). PA-LIRS completely exploits the “recency” and “frequency” information simultaneously to make a replacement decision. PA-LIRS gives a greater probability to clean pages and a smaller probability to dirty pages when evict selection happens. In addition, this proposed algorithm dynamically adjusts the parameter based on the workload pattern to further improve the I/O performance of NAND flash memory. Through a series of comparative experiments on various types of synthetic traces, the results show that PA-LIRS outperforms the previous studies in most cases.

CalmWPC: A buffer management to calm down write performance cliff for NAND flash-based storage systems

NAND Flash-based solid state disks (i.e., SSDs) are widely applied in large-scale storage systems. However, NAND Flash is featured with the asymmetric read and write performance, high erase latency, and the limited number of program/erase cycles (P/Es). Under random write-intensive workloads, a garbage collection (i.e., GC) process inside SSDs causes write performance cliff, which causes high latency for I/O access and degrades SSD lifetime. In real-time transactional applications, such large write performance cliff affects the response time of I/O requests, thereby leading to serious critical errors in real-time applications.To handle this issue, we propose a buffer management strategy called CalmWPC to calm down SSD write performance cliff. CalmWPC seamlessly integrates a data cluster-based data management, a historical access-based prediction algorithm, a semantic fingerprint database. The prediction algorithm checks the future data-cluster activity while classifying the cluster based on its historical write operations. The fingerprint database stores semantic messages for write/update between the buffer and NAND Flash memory. With the fingerprint database in place, CalmWPC calculates the number of invalid data pages in a block in real time. CalmWPC flushes the data cluster into flash memory when the number of update pages reaches a predefined threshold. Our CalmWPC optimizes write performance cliff during GC under random-write workloads.Experimental results reveal that CalmWPC is able to reduce write performance cliff, improve the average latency of user I/Os, and optimize write amplification. Take Financial1 as an example, CalmWPC reduces the write performance cliff by averages of 60.9% and 60.0% compared with LRU and CFLRU. CalmWPC also shortens the response time of LRU and CFLRU by averages of 69.4% and 70.1%, respectively.

Improving Write Performance and Extending Endurance of Object-Based NAND Flash Devices

Write amplification is a major cause of performance and endurance degradations in NAND flash-based storage systems. In an object-based NAND flash device (ONFD), two causes of write amplification are onode partial update and cascading update. Here, onode is a type of small-sized object metadata, and multiple onodes are stored in one NAND flash page. Updating one onode invokes partial page update (i.e., onode partial update), incurring unnecessary migration of the un-updated data. Cascading update denotes updating object metadata in a cascading manner due to object data update or migration. Although there are only several bytes that need to be updated in the object metadata, one or more pages have to be re-written accordingly. In this work, we propose a system design to alleviate the write amplification issue in the object-based NAND flash device. The proposed design includes (1) a multi-level garbage collection technique to minimize unnecessary data migration incurred by onode partial update and (2) a B+ table tree, Semantics-Aware Flexible (SAF) data layout, and selective cache design to reduce the write operations associated with cascading update. To guarantee system consistency, we also propose a power failure handling technique. Experiment results show that our proposed design can achieve up to 20% write reduction compared to the best states of the art.

Data-Pattern-Aware Error Prevention Technique to Improve System Reliability

Program disturb, read disturb, and retention time noise are identified as three major contributors to multilevel cell (MLC) NAND flash memory bit errors. With program/erase cycling and technology scaling, bit error rate (BER) of MLC NAND flash memory rapidly increases. Previous works revealed that BER is heavily dependent on data patterns. Based on this observation, we propose data-pattern-aware (DPA) error protection technique to extend the lifespan of NAND flash-based storage systems. DPA manipulates the ratios of 0’s and 1’s in the stored data to reduce the probability of the data patterns, which are susceptible to device noises. By minimizing the vulnerable data patterns, our scheme can effectively reduce the BER and improves the system endurance. Our DPA scheme also incorporates a data management scheme to minimize the redundancy-induced performance overhead. Simulation results show that our scheme can increase flash system life expectancy by up to $4\times $ .

Data Sorting in Flash Memory

Because flash memory now provides an economical solution for various portable devices and embedded systems, an NAND flash-based storage system has replaced the hard disk drive in many applications. Recently, the implementation of database systems using an NAND flash-based storage system has become an important research topic. In particular, the external sorting is an important operation in database systems. With the very distinctive characteristics of flash memory, the typical external sorting system that adopts a clustered sorting process can result in performance degradation and reduce the reliability of flash memory. In this article, we will propose an unclustered sorting method that considers the unique characteristics of flash memory, and we then propose a decision rule to exploit the advantages of both clustered and unclustered sorting. The decision rule can separate records according to their record length, sort them appropriately by the clustered and unclustered sorting, and merge the sorted results. The experimental results show that the proposed method can improve performance in an NAND flash-based storage system (i.e., solid-state drive).

Resource-aware sector translation layer for resource-sensitive nand flash-based storage systems

As a need for high-density storage capacity increases on many high-end mobile devices such as smartphones, large NAND flash-based storage systems are more commonly used in such smart devices. For these storage systems, however, it becomes a challenge to use large NAND flash without incurring a large system overhead such as a large memory requirement. We propose a novel flash translation layer (FTL), called Resource-Aware Sector Translation Layer (RAST), which is optimized to reduce the memory footprint of an FTL for resource-sensitive storage systems. RAST is based on a hybrid mapping scheme which uses a group of blocks as a unit of mapping so that a small mapping table can cover a large number of blocks. RAST further saves the memory footprint by using an on-demand metadata management scheme which brings only recently accessed metadata into memory. RAST employs a sampling-based wear-leveling scheme which provides competitive wear-leveling performance with very small memory. Our experimental results show that RAST can achieve a good performance level for resource-constraint storage systems with the small memory footprint. For 32 GB NAND flash memory, RAST can achieve the write throughput of up to 57 MB/s using only 34 kB memory.

A technique to improve garbage collection performance for NAND flash-based storage systems

Garbage collection (GC) is a time-consuming operation incorporated in flash memory storage systems, and thus, it has a significant impact on the storage performance. Flash memory provides an internal copy-back operation that can perform page data transfer efficiently during GC. However, this operation is not widely accepted due to some limitations: bit errors can be propagated during the transfer between the pages without being detected, and the operation can be used for blocks within the same plane. In order to address these problems, the page data must be read to a buffer and then transmitted to another page. When this method is used, not only does a temporal overhead occur but also I/O bus utilization and power consumption by the two data transfer operations are increased. In this paper, we propose a technique for reducing the data transfer overhead of GC, using which devices transmit data directly when garbage is collected in a flash memory-based storage system in which several flash memory devices share a single I/O bus, while only the partial updated corrected data is updated when an error is detected. The proposed technique improves the performance of GC and reduces I/O bus utilization compared to the existing methods.

A Concurrency Buffer Control in B-Trees for Flash-Memory Storage Systems

Huge-capacity flash-memory is now an economic solution for various portable devices and embedded systems, a NAND flash-based storage system has replaced a hard-disk drive in many applications. Recently, the implementation of database systems on NAND flash-based storage systems has become an important research topic. In particular, the B-tree index is an important data structure on database systems. With the very distinctive characteristics of flash-memory, previous work focuses on the manipulation of the B-tree index structures but the concurrency buffer control problem in flash-memory storage systems is not addressed. In the paper, we will propose a concurrency buffer control to increase the system throughput when two or more processes could access the same B-tree index structure.

Co-optimization of buffer layer and FTL in high-performance flash-based storage systems

NAND flash-based storage devices have rapidly improved their position in the secondary storage market ranging from mobile embedded systems to personal computer and enterprise storage systems. Recently, the most important issue of NAND flash-based storage systems is the performance of random writes as well as sequential writes, which strongly depends on their two main software layers: a Buffer Management Layer (BML) and a Flash Translation Layer (FTL). The primary goal of our study is to highly improve the overall performance of NAND flash-based storage systems by exploiting the cooperation between those two layers. In this paper, we propose an FTL-aware BML policy called Selective Block Padding and a BML-based FTL algorithm called Optimized Switch Merge, which overcome the limitations of existing approaches on performance enhancement. When using both the proposed techniques, evaluation results show that the throughput is significantly increased over that of previous studies.

Superblock FTL

In NAND flash-based storage systems, an intermediate software layer called a Flash Translation Layer (FTL) is usually employed to hide the erase-before-write characteristics of NAND flash memory. We propose a novel superblock-based FTL scheme, which combines a set of adjacent logical blocks into a superblock. In the proposed Superblock FTL, superblocks are mapped at coarse granularity, while pages inside the superblock are mapped freely at fine granularity to any location in several physical blocks. To reduce extra storage and flash memory operations, the fine-grain mapping information is stored in the spare area of NAND flash memory. This hybrid address translation scheme has the flexibility provided by fine-grain address translation, while reducing the memory overhead to the level of coarse-grain address translation. Our experimental results show that the proposed FTL scheme significantly outperforms previous block-mapped FTL schemes with roughly the same memory overhead.

A multi-channel architecture for high-performance NAND flash-based storage system

Many mobile devices demand a large-capacity and high-performance storage system in order to store, retrieve, and process large multimedia data quickly. In this paper, we present a high-performance NAND flash-based storage system based on a multi-channel architecture. The proposed system consists of multiple independent channels, where each channel has multiple NAND flash memory chips. On this hardware, we investigate three optimization techniques to exploit I/O parallelism: striping, interleaving, and pipelining. By combining all the optimization techniques carefully, our system has shown 3.6 times higher overall performance compared to the conventional single-channel architecture.