NAND Array Research Articles

New program inhibition scheme for high boosting efficiency in three-dimensional NAND array

In this work, program inhibition in a three-dimensional (3D) NAND array has been studied by technology computer-aided design (TCAD) simulation. Results indicate a variation in boosting efficiency among unselected channels with respect to their bias conditions. This variation can cause severe program disturbance in a NAND array. To reduce this potential variation, a new method that guarantees a reliable program inhibition has been designed. With this new scheme, the unwanted threshold voltage (VTH) shift of unselected cells induced by program disturbance can be notably reduced.

Highly Scalable Horizontal Channel 3-D NAND Memory Excellent in Compatibility With Conventional Fabrication Technology

We developed a stacked horizontal channel type floating gate (HC-FG) NAND memory; a 3-D stacked NAND array composed of conventional FG cells. With this cell structure, a wide program/erase (P/E) window is obtained, accompanied by superior read disturb immunity, P/E endurance, and data retention. In addition, we propose a low-cost layer select transistor (LST) that is easily integrated with the HC-FG cell. Because the 3-D memory composed of the HC-FG cell and the LST has good compatibility with conventional fabrication technology, further bit cost scaling is expected.

A high performance NAND array file system based on multiple NAND flash memories

The existing NAND flash memory file systems have not taken into account multiple NAND flash memories for large-capacity storage. In addition, since large-capacity NAND flash memory is much more expensive than the same capacity hard disk drive, it is cost wise infeasible to build large-capacity flash drives. To resolve these problems, this paper suggests a new file system called NAFS for large-capacity storage with multiple small-capacity and low-cost NAND flash memories. It adopts a new cache policy, mount scheme, and garbage collection scheme in order to improve read and write performance, to reduce the mount time, and to improve the wear-leveling effectiveness. Our performance results show that NAFS is more suitable for large-capacity storage than conventional NAND file systems such as YAFFS2 and JFFS2 and a disk-based file system for Linux such as HDD-RAID5-EXT3 in terms of the read and write transfer rate using a double cache policy and the mount time using metadata stored on a separate partition. We also demonstrate that the wear-leveling effectiveness of NAFS can be improved by our adaptive garbage collection scheme.

Investigation of Geometric Effect Impact on SONOS Memory in a NAND Array Structure

Geometric effects on program/erase speeds, endurance, and charge retention of polysilicon-oxide-nitride-oxide-silicon-type memories are investigated with various structures, including Flash cells, capacitors, and NAND array strings of different dimensions. NAND strings with common word-lines or/and bit-lines were employed to characterize the <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$L_{g}$</tex></formula> and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$W$</tex></formula> effect on device performance, which builds up the capability to extrapolate the cell properties of various dimensions. For a charge trapping storage device, it suggests that the evaluation carried out on a large-area device always leads to a conclusion more optimistic than the cell inside array of a real product in all aspects. In addition, a numerical model is proposed to elucidate the observed phenomena from a statistical viewpoint.

Arch NAND Flash Memory Array With Improved Virtual Source/Drain Performance

In this letter, a novel SONOS NAND Flash memory array featuring arch-shaped silicon fin and extended word lines (WL) is proposed to improve virtual source/drain (VSD) performance. The arch shape concentrates electric field, resulting in higher electron concentration at the VSD region and higher on -state cell current. In addition, the extended WL process improves the short-channel-effect (SCE) immunity and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$I$</tex></formula> – <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V$ </tex></formula> characteristics. To verify these, an arch VSD NAND array device was fabricated and characterized. The integrated device shows very small SCE while obtaining high on-state cell current. Program and disturbance characteristics of the device are also confirmed.

Nanoscale Two-bit NAND Silicon-oxide-nitride-oxide-silicon Flash Memories with a Pair of Double Gate FinFET Structures

Novel NAND silicon-oxide-nitride-oxide-silicon (SONOS) flash memories with a pair of double gate (DG) FinFET structures were designed to increase storage density. The proposed structures with two DGs were separated along the length of a Fin and shared a source and a drain with another DG. The proposed memory cell was independently operated as two bits due to the Si-Fin channel with two different doping regions. The process and the device characteristics of the NAND SONOS memory cells were simulated by using technology computer-aided design tools. The programming and erasing characteristics of the NAND array were investigated by using the Fowler-Nordheim tunneling processes. Simulation results showed that the NAND SONOS memories acted as a twobit per cell. The storage capacity of the NAND SONOS memories significantly increased, regardless of the decrease in the cell size.

Reliability improvements in 50 nm MLC NAND flash memory using short voltage programming pulses

For the first time, an innovative programming methodology based on the use of ultra-short voltage pulses is applied in NAND flash architecture. The methodology starts from the physics of SILC dynamics and oxide damage, and relies on the trade-off between duration and amplitude of short voltage programming pulses, minimizing the creation of new traps in the tunnel oxide. The short pulses programming technique is applied on a small 50 nm NAND array designed for multibit application. Benefits of the short-pulse operation lie in that data retention and endurance which show meaningful improvements. The result is relevant for application in multibit technology, and opens the way to more aggressive cell scaling rules.

Embedded TFT nand-Type Nonvolatile Memory in Panel

A new NAND-type nonvolatile memory with a field-enhancing tip structure embedded in low-temperature polycrystalline silicon (LTPS) panel was demonstrated on a glass substrate for the first time. A thin-film transistor (TFT) metal-oxide-nitride-oxide-silicon (MONOS) device based on sequential lateral solidification crystallization with a fully depleted poly-Si channel, an oxide-nitride-oxide stack gate dielectric, and a metal gate is integrated into a NAND array. A NAND test array based on p-channel LTPS TFTs exhibits good cycling endurance and data retention properties and negligible program and read disturbance. These results strongly support the claim that this TFT-MONOS device is a promising candidate for use in embedded nonvolatile memory for system-on-panel and 3-D IC applications

High-K Materials for Nonvolatile Memories

Nonvolatile memories based on charge storage currently dominate the high density data flash market. Multi-level floating gate in NAND array architecture as well as NROM dual bit feature lowest cost per bit and simplicity of processing and thus are likely to have largest market share. For sub 50nm flash scaling introduction of high K dielectrics will be probable. High-K materials allow for improved coupling of the word line to the floating gate still providing sufficiently large physical thickness for reliable retention properties. In this article we review the opportunities and improvements high-K materials can offer for floating gate type devices as well as for charge trapping devices such as SONOS and NROM.

Novel Structures for a 2-Bit per Cell of Nonvolatile Memory Using an Asymmetric Double Gate

A 2-bit operational metal/silicon-oxide-nitride-oxide-silicon (MONOS/SONOS) nonvolatile memory using an asymmetric double-gate (ASDG) MOSFET was studied to double flash memory density. The 2-bit programming and erasing was performed by Fowler-Nordheim (FN) tunneling in a NAND array architecture using individually controlled gates. A threshold voltage shift of programmed states for the 2-bit operation was investigated with the aid of a SILVACO® simulator in both sides of the gate by changing gate workfunctions and tunneling oxide thicknesses. In this paper, the scalability of the device down to 30 nm was demonstrated by numerical simulation. Additionally, guidelines of the 2-bit ASDG nonvolatile memory (NVM) structure and operational conditions were proposed for program, read, and erase.

Multilevel vertical-channel SONOS nonvolatile memory on SOI

A first multilevel vertical-channel silicon-oxide-nitride-oxide-silicon (MLVC-SONOS) memory cell is proposed and fabricated using 0.12-μm silicon-on-insulator (SOI) standard logic process for Flash memory cell with ultrahigh density. If NAND array structure is used, the unit cell size of MLVC-SONOS is 4F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Further reduction of cell size is possible by using the multilevel concept which is originated from the steady states by two carrier transports from both the substrate and the gate. The program threshold voltages and their windows are uniform and controllable depending on the negative gate bias conditions. In addition, we propose a new endurance measurement method for multilevels and report the retention characteristics for multilevel memory operation.

Novel bi-directional tunneling program/erase NOR (BiNOR)-type flash EEPROM

This paper presents a novel flash memory cell, BiNOR, suitable for high-speed, low-power, and high-performance application. The proposed BiNOR structure allows random access, channel Fowler-Nordheim (FN) tunneling program/erase in a NOR-type array (previously, channel FN tunneling program/erase could only be implemented in a NAND array). Using the designated localized P-well structure, BiNOR realizes the hot hole free, low-power bi-directional channel FN tunneling program and erase, and alleviates the oxide instability induced during source erase in the NOR-type flash memory.

Complex 3D CMOS circuits based on a triple-decker cell

Presents circuit design for a three-dimensional (3D) CMOS integrated process. This process, with its three stacked transistor channels, leads to the very efficient basic circuits: inverter, selector, and NAND2. These elements are used to build a complete cell library with standard elements like NORs, latches, flip-flops, etc. Special macro blocks such as multipliers, SRAMs and content addressable memories (CAMs) complete the circuit library. Novel concepts and implementations of three-dimensional prefabricated semicustom arrays are introduced. These are the NAND array and the selector array, for which technology-dependent logic synthesis is investigated. Area requirements for static 3-D CMOS logic ranges from 50% down to 33% compared to two-dimensional (2-D) CMOS. These figures include the wiring and are caused by the transistor stacking and the large number of interconnection layers used in the 3D CMOS process.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Short-Cut Method of Deriving Nearly Optimal Arrays of NAND Trees

Recently, an algorithm has been developed for deriving optimal NAND array realizations of complete Boolean functions [1]. The algorithm has two defects. It often requires a cumbersomely large amount of computations and does not handle incomplete functions. The short-cut method presented here is free from those defects.