N-path Filter Research Articles

N-Path Filtering and Mixing Analysis—A General Approach Based on Fourier Transform

N-Path Filtering and Mixing Analysis—A General Approach Based on Fourier Transform

A 125–600-MHz IF 75-dB DR Partially Time-Interleaved Bandpass DSM Based on Passive N-Path Filters

A 125–600-MHz IF 75-dB DR Partially Time-Interleaved Bandpass DSM Based on Passive N-Path Filters

Discrete-time Receivers, from N-Path to Charge Sharing Band-pass Filters: a Comparison

Technology scaling greatly benefits discrete-time and N-path filters, making them perfect for Software-Defined Radio and wireless Standards designs. Both strategies enable wide-band and narrowband solutions, high selectivity and easy programmability with low power and high linearity. This paper presents a review of discrete-time and N-path based receivers. Their architecture similarities are examined, focusing on discrete-time receiver building blocks whose features and advances are detailed. An extensive literature review of the State-of-the-Art on these strategies is conducted.

Realization of Low-Loss Fully Passive Harmonic Rejection N-Path Filters

This work presents a low-loss fully passive harmonic rejection (HR) N-path filter that performs finite impulse response (FIR) filtering within its core by sequentially charging the baseband capacitors and exploiting combined charge sharing and capacitor stacking techniques. The proposed HR N-path filter achieves an in-band (IB) gain of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 2 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula> 0.5 dB across the 0.25-2 GHz frequency range while consuming 2.3–15.7 mW of power. It achieves an HR ratio (HRR) of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&gt;$</tex-math> </inline-formula> 46/48 dB with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&gt;$</tex-math> </inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula> 8/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula> 11 dBm third/ fifth-order harmonic blocker P1dB.

A Fully Integrated 490-GHz CMOS Receiver Adopting Dual-Locking Receiver-Based FLL

A fully integrated 490-GHz receiver (RX) adopting a dual-locking receiver-based FLL (DL-RBFLL) is presented. The proposed RBFLL structure saves the power consumption by reusing the existing blocks in RX instead of the power-hungry blocks such as dividers and buffers operating at sub-THz. Contrary to the single-loop implementation, the dual-loop RBFLL, which consists of the coarse and fine locking loops, extends the locking range by six times with negligible additional power dissipation. In the RF front-end (FE), the proposed 2nd-order sub-harmonic mixer (SHM) enhances interport isolation and suppresses the undesired LO leakage using a simple passive network. In the IF path, a 2-stage low-noise amplifier (LNA) followed by a 10-stage programmable gain amplifier provides a controllable gain of 0–80 dB with 4-dB step. An N-path filter, which serves as a high-Q bandpass noise filter, improves SNR in the IF path and thus RX sensitivity. Implemented in a 65-nm CMOS, the 490-GHz RX achieves the measured noise figure of 51.1 dB and noise equivalent power (NEP) of 0.85 pW/Hz <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{0.5}$ </tex-math></inline-formula> for the noise bandwidth of 17 MHz. The estimated sensitivity of the proposed RX is −92.9 dBm for a 1 kHz noise bandwidth, which dissipates 31.8 mW from a 1.2-V supply.

Low-Power High-Linearity Mixer-First Receiver Using Implicit Capacitive Stacking With 3× Voltage Gain

In this article, we present a passive mixer-first receiver front end providing a low-power integrated solution for high interference robustness in radios targeting Internet-of-Things (IoT) applications. The receiver front end employs a novel N-path filter/mixer, a linear baseband amplifier, and a step-up transformer to realize sub-6-dB NF and >20-dBm OB-IIP3 concurrently. The proposed N-path filter/mixer exploits an implicit capacitive stacking principle to achieve passive voltage gain of 3 during down-conversion and high out-of-band linearity simultaneously while using at least 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> less total capacitance for the same RF bandwidth compared to a conventional switch-capacitor N-path filter. Fabricated in 22-nm complementary metal–oxide–semiconductor (CMOS) fully depleted silicon on insulator (FDSOI), the receiver prototype—including a 2:6 transformer—occupies only 0.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of active area. Operating in the frequency range of 1.8–2.8 GHz, the front end provides a 45–47-dB conversion gain and a baseband bandwidth of 2 MHz. Due to passive voltage gain in the filter/mixer and transformer, the implemented front end consumes only 1.7–2.5 mW of power to achieve < 6-dB NF, ~24/60/1 dBm out-of-band IIP3/IIP2/B1dB, respectively.

Dual-Band CMOS RF Front-End Employing an Electrical-Balance Duplexer and N-Path LNA for IBFD and FDD Radios

This article proposes a dual-band complementary metal-oxide-semiconductor (CMOS) radio frequency (RF) front end employing a hybrid transformer-based electrical-balance duplexer (EBD) and N-path filter embedded low-noise amplifier (LNA) for both in-band full duplexing (IBFD) and frequency-division duplexing (FDD) radios. To securely obtain sufficient self-interference cancellation (SIC) or transmitter (TX) leakage rejection in IBFD and FDD modes of the EBD at both low-band (LB) (0.7-1 GHz) and mid-band (MB) (1.8-2.2 GHz) frequency ranges, a band-switchable hybrid transformer is designed with a finely adjustable balance network to control the antenna impedance variations. In addition, the four-phase N-path LNA is utilized to further offer TX leakage rejection in the FDD operation. This RF front-end is fabricated using a 65-nm CMOS technology and is mainly characterized by long-term evolution frequency bands. The demonstrated design achieves SIC and TX leakage rejection greater than 55 dB for IBFD and FDD modes of all measured frequency bands, which has a maximum power handling capability of +25 dBm. Furthermore, the design attains voltage gains greater than 8.7 dB for LB and 3.7 dB for MB, noise figures of 10.4 dB for LB and 12.1 dB for MB, out-of-band (OB) P1dBs greater than +21.4 dBm for LB and +21.5 dBm for MB, and OB IIP3s greater than +39.7 dBm for LB and +43.1 dBm for MB. It draws a bias current of 23.8 mA from the LNA and output buffer with a nominal supply of 1.2 V and has an active area of approximately 2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A 0.6-mW 16-FSK Receiver Achieving a Sensitivity of −103 dBm at 100 kb/s

This article presents an RF receiver (RX) designed to exploit the inherent SNR advantage offered by non-coherent 16-FSK modulation relative to more conventional non-coherent modulation schemes, such as FSK and OOK. Specifically, this article demonstrates that when demodulated using two-pole bandpass filters, 16-FSK offers a 4-dB sensitivity advantage compared with binary frequency shift keying (BFSK), at the cost of reduced spectral efficiency at the same data rate. This article then presents the design of a 16-FSK-compatible RX front end, which performs demodulation through 16 N-path filters driven by temperature-stabilized phase-locked loops to ensure calibration-free filter center frequency control, along with augmented Miller capacitors for tight area-constrained bandwidth control. Implemented in 65-nm CMOS, the RX consumes 0.6 mW from a 0.5-V supply while achieving a sensitivity of -103.2 dBm at 100 kb/s, for a power-sensitivity-data-rate figure of merit of 185.2 dB, which represents a 3.2 dB advance over state of the art.

A 0.8V, 152 μW, 433 MHz Mixer-First Receiver with a Self-Adjusted Frequency Tracking Loop

This paper presents a 433 MHz low-power receiver utilizing an N-path filter technique and a self-frequency tracking mechanism. Without the front-end amplifier, the mixer-first architecture can reduce power consumption significantly. A self-adjusted frequency tracking loop (SA-FTL) adjusts local oscillator (LO) frequency to approach input RF frequency automatically, thereby enhancing conversion gain and lowering return loss. The receiver, implemented in a 0.18 μm CMOS process, achieves a sensitivity of -80 dBm at a bit error rate (BER) of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> and a data rate of 10 kb/s, while consuming 152 μW from a 0.8V voltage supply.

Universal Frequency-Domain Analysis of N-Path Networks

N-path commutated capacitive networks provide a practical solution to implement highly sought on-chip high-Q filtering applications in which the use of lumped inductors is undesirable due to their significant footprints and low Q-factors. Recently, it has been also revealed that N-path networks can also exhibit other interesting functionalities, such as nonreciprocal phase-shifting and ultra-wideband true time delay, providing a path to miniaturization of various reciprocal and nonreciprocal devices. The analytical treatment of these networks, however, remains challenging, because their operation involves frequency mixing produced by the time modulation. In this article, we present a highly accurate frequency-domain approach for the analysis of N-path networks based on perturbation theory. Our method compares favorably to the state-of-the-art polyphase analysis by being much simpler mathematically, yet providing results essentially indistinguishable from numerical simulations, while offering physical insights into the N-path filter operation. We particularize the solution for the high-Q operation regime and obtain simple closed-form analytical expressions for harmonic transfer functions, scattering parameters and baseband impedance.

Energy Efficiency Analysis of MIMO Wideband RF Front-End Receivers.

Energy-efficiency is crucial for modern radio-frequency (RF) receivers dedicated to Internet of Things applications. Energy-efficiency enhancements could be achieved by lowering the power consumption of integrated circuits, using antenna diversity or even with an association of both strategies. This paper compares two wideband RF front-end architectures, based on conventional low-noise amplifiers (LNA) and low-noise transconductance amplifiers (LNTA) with N-path filters, operating with three transmission schemes: single antenna, antenna selection and singular value decomposition beamforming. Our results show that the energy-efficiency behavior varies depending on the required communication link conditions, distance between nodes and metrics from the front-end receivers. For short-range scenarios, LNA presents the best performance in terms of energy-efficiency mainly due to its very low power consumption. With the increasing of the communication distance, the very low noise figure provided by N-path LNTA-based architectures outperforms the power consumption issue, yielding higher energy-efficiency for all transmission schemes. In addition, the selected front-end architecture depends on the number of active antennas at the receiver. Hence, we can observe that low noise figure is more important with a few active antennas at the receiver, while low power consumption becomes more important when the number of active RF chains at the receiver increases.

Periodically Time-Varying Noise Cancellation for Filtering-by-Aliasing Receiver Front Ends

This article presents a periodically time-varying (PTV) noise cancellation technique for filtering-by-aliasing (FA) receivers. The key to the proposed technique is the use of a time-varying transconductance (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) cell to sense the noise generated by the PTV resistor in an FA receiver while maintaining the sharp filtering offered by FA. A prototype IC fabricated in a 28-nm CMOS process improves the noise figure (NF) by about 3 dB while achieving over 67-dB stopband rejection with a transition bandwidth (BW) of only four times the RF BW. A minimum in-band NF of 3.2 dB and an average in-band NF of 4.2 dB are demonstrated. With an upfront N-path filter to further enhance the linearity, the measured out-of-band IIP3 is +18 dBm and the blocker 1-dB compression point is +9 dBm. The whole chip, including digital control circuitry, operates under a 0.9-V supply, while consuming 61-mW power at 500-MHz LO.

Expressions for the Harmonic Transfer Functions of N-Path Filters With Arbitrary Source and Load Impedances

We derive analytical expressions for the harmonic transfer functions (HTFs) of N-path filters with arbitrary source and load impedances. We start with first-order approximations of the HTFs based on a simplified “Ohm's-law” characterization of filter operation, and then show how these can be corrected via a feedback visualization to obtain infinite-series expressions. We apply our expressions to study the impact of variations in the source and load impedances. Overall, our approach provides a way to visualize and understand the individual terms contributing to the HTFs and adds to the existing analytical methods to explore N-path filter response.

An N-Path Filter Design Methodology With Harmonic Rejection, Power Reduction, Foldback Elimination, and Spectrum Shaping

In this paper, an adaptive design methodology for synthesizing a harmonic free N-path filter with reduced frequency folding is presented. System level analysis of proposed architecture shows that by adding a few extra paths with proper weights to a conventional N-path filter, several characteristics such as harmonic rejection, power reduction, foldback elimination and spectrum shaping can be achieved. The designed filter is reconfigurable to be a band-pass filter (BPF) or a band-reject filter (notch), based on the requirements. By using the n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> harmonic of Local Oscillator (LO) signal, instead of the fundamental harmonic, the required input clock frequency in N-phase clock generator is reduced by a factor of n. As a proof of concept, a 0.1-5 GHz RF filter with 75 dB and 82 dB harmonic rejection at 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> and 5 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> order harmonics respectively is analyzed and simulated using MATLAB and Cadence Spectre-RF. Post-layout simulations are performed using CMOS 180 nm technology with 1.8 V supply voltage. The total power consumption of the chip is less than 8.5 mW while occupying a silicon area of 0.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Furthermore, Noise Figure (NF) of the circuit is shown to be between 3.5 and 4.7 dB and its out-of-band IIP3 is +6 dBm.

Design of a SAW-less, noise-canceling receiver using an LPTV analysis of a general system with an arbitrary number of N-path filters

This paper, first, presents a Linear Periodically Time-Variant (LPTV) analysis of a general system with an arbitrary number of n-path filters, that the results of mathematical derivations are verified through simulation. Then, a noise-canceling receiver is presented with 3 stages of the 8-path filter. In the structure of this receiver, two filters are used for noise-canceling, and the third filter is used as a Miller bandpass filter to increases the selectivity. The proposed circuit is designed with 65 nm RF CMOS technology and the simulation results show > 44 dB gain, 3–4.5 dB NF, and 0 dBm out-of-band IIP3 at the 50 MHz offset, while in 0.3–3 GHz functional frequency, consuming just 15.52mW of power.

A Higher-Order Highly Linear N-Path Band-Pass Filter

This paper proposes a higher-order fully passive N-path filter (HOFPNF) with better pass-band shape and higher out-of-band rejection compared with the conventional N-path filter. Two band-pass filters with slightly different center frequencies are constructed using two frequency mixers and two complex filters which are completely composed of switches and capacitors. The final output of the HOFPNF can be obtained by subtracting the outputs of these two filters. The input–output characteristic of the proposed filter is derived using the Fourier transform. Comparing the theoretical expressions with Spectre RF PSS-PAC simulation results verifies the correctness of the derived transfer function. The system is realized at TSMC 0.18 µm technology. There is no static power consumption, and the proposed filter represents high linearity, thanks to fully passive implementation. Based on post-layout simulations, the following results are obtained: the − 3 dB bandwidth of 20 MHz, center frequency tunability range of 0.2–1.2 GHz, maximum rejection of 61.8 dB (@ fLO = 500 MHz), 4.5–6.7 dB in-band loss, IIP3 > 17.5 dBm, P1dB > 7.9 dBm and the noise figure (NF) is 6.3–7.5 dB. The dynamic power consumption of the system increases from 2.95 to 19.4 mW by tuning the center frequency at the whole frequency band.

Analysis and Design of N-Path Band-Pass Filters With Negative Base Band Resistance

This paper reviews the possibility of adding an active circuit that implements a small signal negative resistor, to the baseband portion of the N-path filter circuit, in order to compensate for losses that are caused due to harmonic products and other parasitic effects. By adding an active circuit inside the baseband part insertion loss can be eliminated reciprocally. Interestingly, in the case of two-port configuration, in addition to the improvement in insertion loss, a lower noise figure can be theoretically achieved as well. The introduction of the negative resistance is analyzed using linear periodically time-variant theory and linear time invariant approximation. The theoretical analysis is verified in simulation and measurement. The circuit implementation consists of a two-port N-path filter, implemented in a 65-nm CMOS process, with a PMOS cross-coupled pair serving as the negative differential resistor. We achieve $\sim 3.5~dB$ insertion loss improvement at the expense of $0.64~mW$ power addition, at the frequency range of 0.75–2 GHz.

Design and Analysis of Enhanced Mixer-First Receivers Achieving 40-dB/decade RF Selectivity

A “second-order” passive mixer-first receiver is proposed to improve channel selectivity, linearity, and noise figure (NF) in the presence of out-of-band blockers, by presenting an impedance that rolls off at 40 dB/decade as the load to an N-path filter. The synthesis of this impedance is described in a step-by-step manner starting from the required impedance transfer function to its actual circuit realization. Various tradeoffs and limitations of the architecture are described in detail, and layout-related techniques are also provided. Two integrated circuit prototypes were fabricated in 28-nm bulk CMOS as proof of concept for this circuit, including a low-power version. The receiver, capable of broadband operation from 0.2 to 2 GHz, achieves an out-of-band IIP3 of +33 dBm and a blocker P1dB of +12 dBm. Additionally, it achieves an NF of 4.4 dB with less than 2-dB degradation in NF for a 0-dBm blocker.

A Multiband, High-Order Notch Filter for TX Leakage Suppression in FDD Receivers

This letter presents a tunable notch filter that can be reconfigured to improve rejection while offering high power handling. The notch filter uses a series N-path filter in conjunction with an impedance-transformed shunt N-path filter to improve the transmit (TX) rejection or notch concurrent bands. A 4th-order notch provides >40-dB rejection for a single TX channel. In the dual-notch mode, the notches can be tuned to two different TX channels. Finally, a low-power single-notch mode provides >20-dB rejection with low power consumption. The filter is implemented in a 45-nm CMOS SOI process and consumes between 11.9 and 43.9 mW at 1-V supply across a tuning range from 0.45 to 0.9 GHz while providing a peak rejection >50 dB and P1 dB as high as 15.8 dBm.

Synthesis and Design of Enhanced N-Path Filters With 60-dB/decade RF Selectivity

A “third-order” passive mixer-first receiver is presented to improve channel selectivity and resilience to close-in blockers, by building an N-path filter which drives an impedance with 60-dB/decade roll-off. A step-by-step derivation is provided for the synthesis of the first ever driving point impedance with 60-dB/decade roll-off. An integrated circuit prototype was fabricated in 28-nm bulk CMOS as proof-of-concept and characterized. The receiver front-end is capable of broadband operation from 0.2 to 4.5 GHz, demonstrates third-order filtering of close-in blockers, and achieves an out-of-band IIP3 of +21 dBm and B1dB of greater than 6 dBm for blockers at the alternate channel. Additionally, it achieves a noise figure of 6.8 dB in the presence of a 0-dBm blocker.