MOSFET Research Articles

Компьютерное моделирование работы транзисторов и по-лупроводниковых приборов на его основе

The technology of modeling a field-effect transistor in the CAD system COMSOL Multiphysics is considered. The possibilities of CAD, its methods of graphical construction of the model and methods of modeling the behavior of the model are being studied. The object of study is the MOS transistor, its scope, operation and a mathematical model that can be used in designing its operation. The Shikhman-Hodges model, input and output parameters are determined, the degree of its adequacy to a real transistor is set, the main parameters are determined, with the help of which it is possible to conduct a study of a field-effect transistor, its current-voltage characteristic. A transistor model is built in the mode of operation in the mode of small-signal amplifiers, replacing it with a linear four-port model, it is described when this model can be applied when simulating the operation of the device.

The Status of Representative Anode Materials for Lithium‐Ion Batteries

Since the invention of lithium-ion batteries as a rechargeable energy storage system, it has uncommonly promoted the development of society. It has a wide variety of applications in electronic equipment, electric automobiles, hybrid vehicles, and aerospace. As an indispensable component of lithium-ion batteries, anode materials play an essential role in the electrochemical characteristics of lithium-ion batteries. In this review, we described the development from lithium-metal batteries to lithium-ion batteries in detail on the time axis as the first step; This was followed by an introduction to several commonly used anode materials, including graphite, silicon, and transition metal oxide with discussions the charge-discharge mechanism, challenges and corresponding strategies, and a collation of recent interesting work; Finally, three anode materials are summarized and prospected. Hopefully, this review can serve both the newcomers and the predecessors in the field.

An area-efficient sub-10 nW temperature-to-digital converter for thermopile temperature sensors

A 6.29 nW temperature-to-digital converter for IR radiation-based thermopile temperature sensors was designed and fabricated on the chip area of 0.068 mm2 using 90 nm CMOS technology. The sub-mV voltage produced by the sensor is nearly proportional to the temperature difference between the object and the environment and is converted to sub-nA current using the gate-leakage characteristics of PMOS transistors. The ratio of the sub-nA current and the reference current proportional to the sub-mV voltage difference is converted to the frequency ratio of the two current-to-frequency oscillators. Then, the digital output proportional to the tiny voltage difference can be obtained by the counters. After the two-point calibrated digital outputs are mapped to the object temperatures, the average resolution is 0.11 °C with a conversion time of 348 ms, which results in the figure of merit of 0.026 nJ × °C2. The inaccuracy of the object temperature is +0.26/−0.95 °C from −10 °C to 100 °C at the ambient temperature of 25 °C.

Analysis of Device Mismatches Effect on the Performance of UWB Receiver Front-End in Wireless Body Area Network Sensor Nodes

Today it is important to manufacture high quality integrated circuits which are insensitive to device mismatches. This paper presents an analysis of MOSFET transistors mismatches effect on the performance of UWB receiver front-end which constitute the most important part of Wireless Body Area Network sensor node. The receiver is based on Balun LNA with 25% fully differential double-balanced passive mixer. A PMOS and NMOS transistors mismatch models were proposed to determine LNA output offset voltage and mixer offset current respectively. The analysis result suggests that, to minimize NMOS current mismatch, and thus reducing second-order inter modulation distortion, the overdrive voltage must be maximized. A Monte Carlo and harmonic balance simulations were performed using 0.18µm CMOS process to evaluate the impact of mismatch as well as Vth mismatch on the receiver gain and IIP2. Simulation results show that IIP2 of the receiver is less sensitive to mixer NMOS mismatch but receiver gain is more sensitive. The receiver IIP2 confidence interval in case of NMOS mismatch is [24.674, 24.77]dBm and in case of NMOS Vth mismatch is [24.659, 24.857]dBm. This show the robustness of the proposed UWB receiver front end. Therefore the proposed circuit meets the requirement of UWB system perfectly which make it suitable for WBAN applications.

The Research of Integrated Circuit Design Technology

This article discusses the fundamentals of analogue integrated circuit design and construction, as well as the operation and some basic models of MOS transistors. It also provides a thorough introduction to the CMOS, PMOS, and NMOS structures, as well as the benefits and drawbacks of each. Additionally, operational and differential amplifiers are introduced, along with some examples of their uses. While attending summer school, I also learned how to simulate the SPEICE model using the computer program CoolSPICE. The SPEICE model is a literal description of a circuit component that theoretically predicts the behavior of that component under various conditions. The article ends with forecasts and suggestions regarding the future evolution of analog circuits and their potential effects on society.

PERFORMANCE ANALYSIS OF ON CHIP INTERCONNECTS FOR ASIC DESIGN

Abstract—Circuit complexity and performance have in- creased as a result of the constant reduction in semicon- ductor device feature size. Improved area, power, and speed have resulted from scaling the lateral dimensions of planar devices like MOS transistors. Current scaling patterns hurt interconnects unique properties, especially the global lines. These lengthy resistive cables now consume more electricity and have slower signal propagation times. The connection models must now take inductive effects into account for potential inclusion. Due to these factors, precise interconnect models for on-chip devices are necessary to ascertain the signal properties and construction specifications of fast DSM interconnect. The purpose of this project is to enlighten on the difficulty in designing on-chip connections, particularly for extremely fast purposes. Index Terms—DSM, Interconnects, Integrated Circuits (ICs)

A Physics-Based Compact Model to Capture Cryogenic Behavior of LDMOS Transistors

In this work, a detailed characterization of lateral DMOS transistors in the cryogenic regime is carried out. It is shown that carrier freeze-out in the drift region is responsible for increased ON-resistance for temperatures lower than a transition temperature, which is independent of device dimensions. The carrier freeze-out affects the operation of laterally diffused MOS (LDMOS) transistors in the linear region but not in the saturation region due to field-assisted ionization. A peak behavior in output conductance is also observed at cryogenic temperatures. The physics behind these observed anomalous behaviors is studied in detail and modeled. The industry-standard HiSIM_HV2 model is augmented with new equations to extend the model accuracy to 77 K. The accuracy of the model is verified with the data measured from LDMOS transistors with different dimensions. The model accurately captures the device behavior in the 77–300 K temperature range and demonstrates excellent scalability.

Improvements in 2D p-type WSe2 transistors towards ultimate CMOS scaling

This paper provides comprehensive experimental analysis relating to improvements in the two-dimensional (2D) p-type metal–oxide–semiconductor (PMOS) field effect transistors (FETs) by pure van der Waals (vdW) contacts on few-layer tungsten diselenide (WSe2) with high-k metal gate (HKMG) stacks. Our analysis shows that standard metallization techniques (e.g., e-beam evaporation at moderate pressure ~ 10–5 torr) results in significant Fermi-level pinning, but Schottky barrier heights (SBH) remain small (< 100 meV) when using high work function metals (e.g., Pt or Pd). Temperature-dependent analysis uncovers a more dominant contribution to contact resistance from the channel access region and confirms significant improvement through less damaging metallization techniques (i.e., reduced scattering) combined with strongly scaled HKMG stacks (enhanced carrier density). A clean contact/channel interface is achieved through high-vacuum evaporation and temperature-controlled stepped deposition providing large improvements in contact resistance. Our study reports low contact resistance of 5.7 kΩ-µm, with on-state currents of ~ 97 µA/µm and subthreshold swing of ~ 140 mV/dec in FETs with channel lengths of 400 nm. Furthermore, theoretical analysis using a Landauer transport ballistic model for WSe2 SB-FETs elucidates the prospects of nanoscale 2D PMOS FETs indicating high-performance (excellent on-state current vs subthreshold swing benchmarks) towards the ultimate CMOS scaling limit.

High Ion/Ioff ratio 4H-SiC MISFETs with stable operation at 500 °C using SiO2/SiNx/Al2O3 gate stacks

In this work, 4H-SiC lateral metal-insulator-semiconductor field-effect transistors (MISFETs) were demonstrated to operate up to 500 °C with a high on/off current ratio (over 109). A low off-state current of 3.6 × 10−9 mA/mm at 500 °C was obtained in SiC MISFET with a ring structure. The MISFETs with SiO2/SiNx/Al2O3 gate dielectric stack showed minimum subthreshold swings of 155 and 240 mV/dec at room temperature and 500 °C, respectively, indicating good thermal stability of this gate dielectric stack on SiC. An interface trap density of 1.3 × 1011 cm−2 eV−1 at E − EV = 0.2 eV was extracted from the Capacitance–Voltage (CV) measurements at room temperature, which confirms excellent dielectric interface. The electron mobility increases with increasing temperature and reaches 39.4 cm2/V s at 500 °C. These results indicate that SiC MISFETs with triple layer dielectrics and ring structure have a high potential in extreme-temperature electronics.

Novel tunable current feedback instrumentation amplifier based on BBFC OP-AMP for biomedical applications with low power and high CMRR

The paper presents a novel low power, low noise and high CMRR current feedback instrumentation amplifier (CFIA) design for biomedical signal acquisition i.e. EEG/ECG applications is presented. The proposed instrumentation amplifier performance is evaluated using 0.18μm, CMOS technology with 1.8 V supply and results are obtained in Cadence EDA tool. The proposed CFIA is implemented using a dual output bandwidth boosted folded cascode operational amplifier (BBFC OP-AMP) active block. In this paper the proposed CFIA performance parameters has been considered for optimization to get better results by using the idea of signal to noise ratio (SNR) with Taguchi design of experiments (Taguchi DoE) and analysis of variance (ANOVA) to estimate the most important independent variable which control the performance of the design. The bias voltage, channel length and width of input MOS transistors have been selected to optimize the proposed circuit performance. The proposed CFIA structure have 50.33 to 69.67 dB tunable differential gain, common mode rejection ratio (CMRR) of 143.19 dB, tunable bandwidth of 148.24 kHz to 1.31 MHz, dynamic range (DR) of 74.31 dB and 297.73 dB of figure of merit (FoM). The CFIA shows an equivalent input referred noise (IRN) of 0.586 μV at 0.1 Hz to 148.24 kHz frequency range, with total power dissipation of 102.73 μW and occupies 8194μm2 of core area. The simulation results of the proposed CFIA are close to the predicted solution obtained from ANOVA. The PVT analysis and post layout simulation has been performed to check the robustness of the proposed design. The proposed design has been compared with the other existing literature which shows the competence of the design.

CMOS-based area-and-power-efficient neuron and synapse circuits for time-domain analog spiking neural networks

Conventional neural structures tend to communicate through analog quantities, such as currents or voltages; however, as CMOS devices shrink and supply voltages decrease, the dynamic range of voltage/current-domain analog circuits becomes narrower, the available margin becomes smaller, and noise immunity decreases. More than that, the use of operational amplifiers (op-amps) and continuous-time or clocked comparators in conventional designs leads to high energy consumption and large chip area, which would be detrimental to building spiking neural networks. In view of this, we propose a neural structure for generating and transmitting time-domain signals, including a neuron module, a synapse module, and two weight modules. The proposed neural structure is driven by a leakage current of MOS transistors and uses an inverter-based comparator to realize a firing function, thus providing higher energy and area efficiency compared to conventional designs. The proposed neural structure is fabricated using a TSMC 65 nm CMOS technology. The proposed neuron and synapse occupy the area of 127 and 231 μm2, respectively, while achieving millisecond time constants. Actual chip measurements show that the proposed structure implements the temporal signal communication function with millisecond time constants, which is a critical step toward hardware reservoir computing for human–computer interaction. Simulation results of the spiking neural network for reservoir computing with the behavioral model of the proposed neural structure demonstrates the learning function.

Polymorphic Hybrid CMOS-MTJ Logic Gates for Hardware Security Applications

Various hardware security concerns, such as hardware Trojans and IP piracy, have sparked studies in the security field employing alternatives to CMOS chips. Spintronic devices are among the most-promising alternatives to CMOS devices for applications that need low power consumption, non-volatility, and ease of integration with silicon substrates. This article looked at how hardware can be made more secure by utilizing the special features of spintronics devices. Spintronic-based devices can be used to build polymorphic gates (PGs), which conceal the functionality of the circuits during fabrication. Since spintronic devices such as magnetic tunnel junctions (MTJs) offer non-volatile properties, the state of these devices can be written only once after fabrication for correct functionality. Symmetric circuits using two-terminal MTJs and three-terminal MTJs were designed, analyzed, and compared in this article. The simulation results demonstrated how a single control signal can alter the functionality of the circuit, and the adversary would find it challenging to reverse-engineer the design due to the similarity of the logic blocks’ internal structures. The use of spintronic PGs in IC watermarking and fingerprinting was also explored in this article. The TSMC 65nm MOS technology was used in the Cadence Spectre simulator for all simulations in this work. For the comparison between the structures based on different MTJs, the physical dimension of the MTJs were kept precisely the same.

Food-Grade Metal Oxide Nanoparticles Exposure Alters Intestinal Microbial Populations, Brush Border Membrane Functionality and Morphology, In Vivo (Gallus gallus).

Among food additive metal oxide nanoparticles (NP), titanium dioxide (TiO₂) and silicon dioxide (SiO₂) are commonly used as food coloring or anti-caking agents, while zinc oxide (ZnO) and iron oxide (Fe₂O₃) are added as antimicrobials and coloring agents, respectively, and can be used as micronutrient supplements. To elucidate potential perturbations associated with NP consumption on gastrointestinal health and development, this in vivo study utilized the Gallus gallus (broiler chicken) intraamniotic administration to assess the effects of physiologically relevant concentrations of food-grade metal oxide NP on brush border membrane (BBM) functionality, intestinal morphology and intestinal microbial populations in vivo. Six groups with 1 mL injection of the following treatments were utilized: non-injected, 18 MΩ DI H2O; 1.4 × 10-6 mg TiO2 NP/mL, 2.0 × 10-5 mg SiO2 NP/mL, 9.7 × 10-6 mg ZnO NP/mL, and 3.8 × 10-4 mg Fe2O3 NP/mL (n = 10 per group). Upon hatch, blood, cecum, and duodenum were collected to assess mineral (iron and zinc) metabolism, BBM functional, and pro-inflammatory-related protein gene expression, BBM morphometric analysis, and the relative abundance of intestinal microflora. Food additive NP altered mineral transporter, BBM functionality, and pro-inflammatory cytokine gene expression, affected intestinal BBM development and led to compositional shifts in intestinal bacterial populations. Our results suggest that food-grade TiO₂ and SiO₂ NP have the potential to negatively affect intestinal functionality; food-grade ZnO NP exposure effects were associated with supporting intestinal development or compensatory mechanisms due to intestinal damage, and food-grade Fe₂O₃ NP was found to be a possible option for iron fortification, though with potential alterations in intestinal functionality and health.

Electronically Tunable Memristor Emulator Implemented Using a Single Active Element and Its Application in Adaptive Learning.

In recent times, much-coveted memristor emulators have found their use in a variety of applications such as neuromorphic computing, analog computations, signal processing, etc. Thus, a 100 MHz flux-controlled memristor emulator is proposed in this research brief. The proposed memristor emulator is designed using a single differential voltage current conveyor (DVCC), three PMOS transistors, and one capacitor. Among three PMOS transistors, two transistors are used to implement an active resistor, and one transistor is used as the multiplier required for the necessary memristive behaviors. Through simple adjustment of the switch, the proposed emulator can be operated in incremental as well as decremental configurations. The simulations are performed using a 180 nm technology node to validate the proposed design and are experimentally verified using AD844AN and CD4007 ICs. The memristor states of the proposed emulator are perfectly retained even in the absence of external stimuli, thereby ascertaining the non-volatility behavior. The robustness of the design is further analyzed using the PVT and Monte Carlo simulations, which suggest that the circuit operation is not hindered by the mismatch and process variations. A simple neuromorphic adaptive learning circuit based on the proposed memristor is also designed as an application.

Experimental investigation into impacts of neutron irradiation on pMOS dosimeter behaviors

The p-channel metal–oxide–semiconductor (pMOS) transistor is a frequently used dosimeter for ionizing radiation, such as γ-rays, since its threshold voltage changes (ΔVth) in proportion to the ionization dose. When a pMOS is subjected to γ-ray and neutron radiation fields, the neutrons can influence the ΔVth response to γ-rays. Individual cobalt-60 γ-ray irradiation and sequential irradiation by fission neutrons and subsequent cobalt-60 γ-rays are used to explore the neutron-induced impacts. Experiments show that preceding neutron irradiation can reduce γ-ray sensitivity of ΔVth while accelerating the recovery of ΔVth during the post-γ-irradiation annealing. Additionally, the component of ΔVth induced by oxide charges (ΔVox) is separated from that induced by interface traps as determined by mid-gap tests. This proves that the neutron sensitivity of ΔVox accounts for that of ΔVth. According to nuclear collision theory, this work suggests that the electronic loss of neutrons rather than the nuclear loss dominates the neutron-induced influences on ΔVth.

A 211-to-263-GHz Dual-LC-Tank-Based Broadband Power Amplifier With 14.7-dBm P SAT and 16.4-dB Peak Gain in 130-nm SiGe BiCMOS

This article presents a broadband sub-terahertz (THz) power amplifier (PA) with a low-loss four-way power combiner. The proposed power combiner consists of an improved zero-degree combiner (ZDC) and a three-conductor Marchand balun simultaneously achieving broadband matching and power combining. The proposed three-conductor Marchand balun adopts a dual- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$LC$ </tex-math></inline-formula> tank technique by merging two resonators, and it can be equivalent to a transformer-based multi-resonating network. The power distribution is realized by one input power splitter generating two pairs of differential signals and two parallel 1-to-2 active power splitters. This hybrid distribution driving network further enhances efficiency and power gain. Based on these improvements, a high-output-power sub-THz PA with superior efficiency has been fabricated in the 130-nm SiGe bipolar complementary metal oxide silicon field effect transistor (BiCMOS) technology. The three-stage PA achieves a peak power gain of 16.4 dB, 3-dB small-signal gain bandwidth of 52 GHz from 211 to 263 GHz, a measured maximum saturated output power of 14.7 dBm at 224 GHz, and a peak power-added efficiency (PAE) of 3.13% at 220 GHz. The folded input splitter and extremely compact power combining methodology lead to a core area of 770 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}\,\,\times \,\,280\,\,\mu \text{m}$ </tex-math></inline-formula> .

An Edge-Combining Frequency-Multiplying Class-D Power Amplifier

The class-D power amplifier (PA) is commonly implemented in CMOS, but its operating frequency is often limited due to the power loss of parasitic capacitances and the lower transition frequency of the PMOS transistor. In this brief we demonstrate edge-combining frequency-multiplication embedded directly in the output-stage, allowing higher-frequency operation of the class-D PA, while maintaining similar performance to a lower-frequency PA. A 65nm CMOS prototype achieves output power and system efficiency of 22.3dBm and 30.2%, respectively. The prototype is tested with a D-BPSK signal and achieves an EVM of 2%-rms. Although the prototype was not embedded with amplitude modulation capability, it can be readily adapted for such operation using switched-capacitor PA techniques.

A W-Band Vector Modulator Using Short-Channel Transistor Current Sources and Impedance Compensation Varactors

A W-band vector modulator based on vector summing with a Gilbert-cell is presented, in which two kinds of error-reducing schemes are applied to the summing circuit. One is to use current sources made of short channel transistors to take advantage of the channel length modulation effect. The other is to introduce impedance correction varactors at the input. It controls both gain and phase by using a digital-to-analog converter (DAC) which is designed to make the output impedance of the summing circuit constant regardless of states. The intrinsic gain and phase errors are also analyzed with the help of a simple current model of a MOS transistor, which explains the error-reducing schemes. It was implemented in 28-nm CMOS technology, which consumes only 7.7mA of DC and occupies an area of 0.11mm2 (excluding pads). The RMS gain error of 0.1dB and the RMS phase error of 1.3° were measured with 4-bit gain and 6-bit phase controls at 94 GHz, where the gain dynamic range was around 15 dB.

A Reliability-Enhanced Differential Sensing Amplifier for Hybrid CMOS/MTJ Logic Circuits

Recently, hybrid logic circuits based on magnetic tunnel junctions (MTJs) have been widely investigated to realize zero standby power. However, such hybrid CMOS/MTJ logic circuits suffer from a severe sensing reliability due to the limited tunnel magnetoresistance ratio (TMR ≤ 150%) of the MTJ and the large process variation in the deep sub-micrometer technology node. In this paper, a novel differential sensing amplifier (DSA) is proposed, in which two PMOS transistors are added to connect the discharging branches and evaluation branches. Owing to the positive feedback realized by these two added PMOS transistors, it can achieve a large sensing margin. By using an industrial CMOS 40 nm design kit and a physics-based MTJ compact model, hybrid CMOS/MTJ simulations have been performed to demonstrate its functionality and evaluate its performance. Simulation results show that it can achieve a smaller sensing error rate of 9% in comparison with the previously proposed DSAs with a TMR ratio of 100% and process variation of 10%, while maintaining almost the same sensing delay of 74.5 ps and sensing energy of 1.92 fJ/bit.

A Real-Time Electronically Tunable All-MOS Universal Biquadratic Voltage-Mode Filter

— In this paper, an electronically tunable universal biquadratic voltage-mode filter that is based only on MOS transistors is proposed. Configuration of the proposed filter is simple and there is no need to use component matching. Since the proposed filter contains only MOS transistors, it is very suitable for implementation in system-on-chip (SoC) applications. The cutoff frequency of the lowpass (LP) and highpass (HP) filters as well as the center frequency and the bandwidth of the bandpass (BP) and bandstop (BS) filters can be controlled either in a continuous range or in a discrete manner by means of a digital control word. Besides, the filter type can be changed during the real time by an appropriate code. Operation of all the filtering functions are verified by simulation using the Berkeley predictive-technology models (BPTM) of the 130 nm complementary metal-oxide semiconductor (CMOS) technology with power-supply voltage, VDD, of 1.2 V. The proposed filter is analyzed quantitatively, and the effects of the total-harmonic distortion (THD), noise, process, voltage and temperature (PVT) variations are also investigated. The average power consumption of the LP, HP, BP, BS, and allpass (AP) filters are found to be 30, 118, 74, 118, and 30 (all in µW). The price paid for all these advantages is more sensitivity to process variations for the lowpass filter.