N-modular Redundancy Research Articles

Neutron Cross-Section of N-Modular Redundancy Technique in SRAM-Based FPGAs

In this paper the fault-masking capability of N-modular redundancy systems synthesized into SRAM-based FPGAs is evaluated. In the proposed N-modular technique an original self-adaptive majority voter elects the outputs of the redundant modules. Experimentally evaluated neutron cross-section, area, and power consumption were analyzed for different numbers of redundant modules, ranging from 3 copies (standard TMR) up to 7 copies.

Fault-tolerant Gaussian normal basis multiplier over GF(2 m )

Fault-tolerant design of a finite field multiplier is an efficient method for resisting fault-based cryptanalysis in Elliptic curve cryptosystems. A novel fault-tolerant bit-parallel Gaussian normal basis (GNB) multiplier with type-t over GF(2m), which can tolerate multiple module failures at one time, is presented. No hardware modification in the proposed GNB multiplier is required to achieve the fault-tolerant function. Hence, the proposed fault-tolerant GNB multiplier has low hardware cost. The reliability of the proposed fault-tolerant GNB multiplier with type-t increases as t increases. However, the behaviour of existing GNB multipliers with concurrent error correction (CEC) resembles triple modular redundancy (TRM) when t>3. In practice, most of suggested m's by NIST use GNB with type-t>3. The proposed fault-tolerant GNB multiplier is an N-modular redundancy (NMR) system with N=t. Thus, the proposed fault-tolerant GNB multiplier with type-t can tolerate at most t/2-1 failed modules simultaneously, while existing GNB multipliers with CEC only can tolerate one failed module. The proposed GNB multiplier requires less extra space and time complexities than similar multipliers. System reliability of the proposed fault-tolerant GNB multiplier is better than that of similar GNB multipliers.

Soft N-Modular Redundancy

Achieving robustness and energy efficiency in nanoscale CMOS process technologies is made challenging due to the presence of process, temperature, and voltage variations. Traditional fault-tolerance techniques such as N-modular redundancy (NMR) employ deterministic error detection and correction, e.g., majority voter, and tend to be power hungry. This paper proposes soft NMR that nontrivially extends NMR by consciously exploiting error statistics caused by nanoscale artifacts in order to design robust and energy-efficient systems. In contrast to conventional NMR, soft NMR employs Bayesian detection techniques in the voter. Soft voter algorithms are obtained through optimization of appropriate application aware cost functions. Analysis indicates that, on average, soft NMR outperforms conventional NMR. Furthermore, unlike NMR, in many cases, soft NMR is able to generate a correct output even when all N replicas are in error. This increase in robustness is then traded-off through voltage scaling to achieve energy efficiency. The design of a discrete cosine transform (DCT) image coder is employed to demonstrate the benefits of the proposed technique. Simulations in a commercial 45 nm, 1.2 V, CMOS process show that soft NMR provides up to 10× improvement in robustness, and 35 percent power savings over conventional NMR.

Reliability Impact of N-Modular Redundancy in QCA

Nanoelectronic systems are extremely likely to demonstrate high defect and fault rates. As a result, defect and/or fault tolerance may be necessary at several levels throughout the system. Methods for improving defect tolerance, in order to prevent faults, at the component level for quantum-dot cellular automata (QCA)1 have been studied. However, methods and results considering fault tolerance in QCA have received less attention. In this paper, we present an analysis of how QCA system reliability may be impacted by using various N-modular redundancy (NMR) schemes. Our results demonstrate that using NMR in QCA can improve reliability in some cases, but can harm reliability in others.

Novel hazard-free majority voter for N -modular redundancy-based fault tolerance in asynchronous circuits

N -modular redundancy (NMR) is the simplest and most effective fault-tolerant design method for integrated circuits, where N copies of a circuit are employed and a majority voter produces the voted output. Asynchronous circuits, however, exhibit various characteristics that limit the applicability of NMR. Specifically, the hazard-free property of the output in these circuits must be preserved when hardware providing fault tolerance, such as a majority voter, is added. In this work, we first demonstrate that a typical majority voter design would fail to preserve the hazard-free property of its response. We then propose a hazard-free majority voter design for the triple-modular redundancy fault-tolerance design paradigm, which enters an output-holding state to preserve the output value when transient errors may be sensitised to its inputs. By exploring various conditions to exit from the output-holding state, we describe several extensions of the voter into an NMR one, each yielding a distinct implementation with different tolerance characteristics and area cost. We generalise this extension based on the exit condition and analyse the associated tolerance capability of the extended NMR voter. Finally, the proposed hazard-free voter is simulated using HSPICE, and detailed area cost formulations are derived for the proposed voter designs.

DEPENDABILITY ANALYSIS OF HYBRID REDUNDANCY SYSTEMS USING FUZZY APPROACH

With the increasing demand for high reliability in mission critical systems such as space shuttle, digital flight and real time control to mention a few, reliability analysis of fault tolerant systems continues to be the focus of most researchers. The reliability analysis of triple modular redundancy (TMR) and hybrid redundancy (TMR with spares) systems is in general carried out with the assumption of failure rate being precise. However, in practice failure rate is imprecise due to the uncertainties of system operation. In this paper, the dependability analysis of hybrid redundancy systems (HRS) comprising of N-modular redundancy (NMR) and standby redundancy is presented assuming failure rates and repair rates as fuzzy numbers. Each module of the NMR is assumed to have access to a number of cold spares and a repair facility. A Markov model for the HRS is developed. As the Markov model parameters may not be precisely known due to various reasons, vertex method and α-cut method is applied. These methods allow uncertainty-based parameters that are represented as fuzzy numbers. The dependability measures such as availability and reliability are obtained. A comparative study of the fuzzy results and the conventional results using probability concepts is presented.

Dependability modeling and analysis of hybrid redundancy systems

PurposeThe aim of this study is to demonstrate that hybrid redundancy systems are superior to the conventional N‐modular redundancy (NMR) systems.Design/methodology/approachThe hybrid redundancy system is a synthesis of the NMR system and the standby redundancy. Each module of the NMR has access to k cold spares (k<N) and a repair facility. A semi‐Markov model for the hybrid redundancy system is developed and transient analysis is performed.FindingsSome dependability measures such as availability, reliability, mean time to failure and steady‐state availability are obtained.Originality/valueThis paper presents the transient analysis of the hybrid redundancy systems. The results obtained will be useful to reliability engineers and reliability practitioners.

Triple modular redundancy

In computing, triple modular redundancy (TMR) is a fault tolerant form of N-modular redundancy, in which three systems perform a process and that result is processed by a voting system to produce a single output. If any one of the three systems fails, the other two systems can correct and mask the fault. If the voter fails then the complete system will fail. However, in a good TMR system the voter is much more reliable than the other TMR components. Alternatively, if there is another stage of TMR logic following the current one (for example, in systems such as the Saturn Launch Vehicle Digital Computer), then three voters are used - one for each copy of the next stage of logic.

Reliability-Driven Gate Replication for Nanometer-Scale Digital Logic

To make digital circuits with unreliable devices more reliable has been a design challenge, especially for today's nanometer-scale technologies. In this paper, we discuss gate replication architecture towards increasing the reliability of individual logic gates. While this architecture is similar to, and a special case of, conventional N-modular redundancy scheme, we provide more interpretation and extend it to the situation where N is an even integer by using threshold logic gate instead of majority voter. We also study the reliability models for generic gates with single-electron tunneling (SET) technology. Both analysis and numerical evaluation suggest that while more redundancy leads to higher reliability in general, the improvement rate depends on individual gate failure rates

Replication Cache: A Small Fully Associative Cache to Improve Data Cache Reliability

Soft error conscious cache design has become increasingly crucial for reliable computing. The widely used ECC or parity-based integrity checking techniques have only limited capability in error detection and correction, while incurring nontrivial penalty in area or performance. The N modular redundancy (NMR) scheme is too costly for processors with stringent cost constraints. This paper proposes a cost-effective solution to enhance data reliability significantly with minimum impact on performance. The idea is to add a small fully associative cache to store the replica of every write to the L1 data cache. Due to data locality and its full associativity, the replication cache can be kept small while providing replicas for a significant fraction of read hits in L1, which can be used to enhance data integrity against soft errors. Our experiments show that a replication cache with eight blocks can provide replicas for 97.3 percent of read hits in L1 on average. Moreover, compared with the recently proposed in-cache replication schemes, the replication cache is more energy efficient, while improving the data integrity against soft errors significantly.

Construction of a fault‐tolerant voter for N‐modular redundancy

AbstractThis paper proposes a method of improving the reliability of the voter in N‐modular redundancy systems. TMR and other multiplexing techniques were developed to improve the voter's reliability. However, in such techniques, the output of multiplexed voters must be determined by majority voting. In this study, the reliability of the voter is improved by means of ADR, a temporal redundancy technique. An ADR system normally includes an encoder, an ADR‐applied circuit, a decoder, and an error detector. However, previous studies have dealt only with the configuration of ADR‐applied circuits. This study considers the configuration of the entire ADR system, and the feasibility of a doubled‐circuit configuration is proven. In addition, the proposed method is verified to improve the reliability of voters in N‐modular redundancy systems. © 2004 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 87(12): 62–71, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002sol;ecjb.20136

Beyond the conventional techniques of software fault tolerance

This short article describes a low cost and unconventional technique for gaining software fault tolerance without using N-modular redundancy in both hardware and software.

THE DESIGN AND IMPLEMENTATION OF A CUSTOMIZABLE FAULT TOLERANCE FRAMEWORK

While there have been significant advances in fault tolerance research, the effort has focused on the design of individual fault-tolerant systems or methodologies. Recently, some research has been initiated to develop techniques that can provide a spectrum of fault tolerance capabilities. In this paper, we present the design of a fault tolerance framework that can support a wide range of applications with various fault tolerance requirements, various criticality levels, and various system models. The framework is designed to be parameterizable so that the user can configure it to obtain the desired features. Also, the framework is designed to be an off-the-shelf component such that application programs can be integrated within it easily to obtain the fault-tolerant version of the application system. A specialized N-modular redundancy (SNMR) scheme has been developed to serve as the primary approach for achieving efficient and cost-effective fault tolerance for the framework. In most cases, the SNMR scheme yields better performance and lower cost in providing fault tolerance as compared with conventional NMR schemes. It also enhances the scalability and customizability of the general replication method. This paper discusses the main issues in the design and implementation of the SNMR framework, including the major concept of the SNMR framework, various SNMR algorithms that tolerate various types of faults, an object-oriented overall system design and the interface protocol class hierarchy. The interface protocol class hierarchy provides a nice paradigm for the implementation of customizable, highly reusable, and easily extensible SNMR framework.

Software tool combining fault masking with user-defined recovery strategies

The voting farm, a tool which implements a distributed software voting mechanism for a number of parallel message passing systems, is described. The tool, developed in the framework of EFTOS (embedded fault tolerant supercomputing), can be used in stand-alone mode or in conjunction with other EFTOS fault tolerance tools. In the former case, exploitation of the mechanism is described, e.g. to implement restoring organs (N-modular redundancy systems with N-replicated voters); in the latter case, it is shown how it is possible for the user to implement in an easy and effective way a number of different recovery strategies via a custom, high-level language. Combining such strategies with the basic fault masking capabilities of the voting tool makes it possible to set up complex fault tolerant systems such as, for instance, N-and-M-spare systems or gracefully degrading voting farms. The impact that the tool can have on reliability is discussed, and it is shown how, besides structural design goals like fault transparency, the tool achieves replication transparency, a high degree of flexibility and ease-of-use, and good performance.

Fault tolerant arithmetic unit using duplication and residue codes

This paper is a study of the practical value of the various approaches, proposed so far, to achieve fault tolerance in arithmetic units using the residue code technique and to find the best design in terms of cost and error coverage. The results have shown that the error correction approaches can treat a one-bit error ( E = ± 2 i ) using relatively small hardware cost and time delay. It is also shown that no more than a single error, of the one-bit type, can be treated at reasonable cost using error correction approaches. However, a combination of N-modular redundancy (NMR) and residue codes can be used to cover a wide range of errors at considerably lower cost. Here we suggest anapproach based on model duplication and residue codes (DAR) which is shown to have better error coverage than error correction approaches and lower cost than both triple modular redundancy (TMR) and error correction approaches.

Fault Tolerance with Multiple Task Modular Redundancy

The redundant units in a classic N Modular Redundancy (NMR) system are employed solely for fault tolerance, making this technique inefficient. This paper introduces Multiple Task Modular Redundancy that allows an NMR system to have a higher throughput by exploiting, when no faults have occurred, the system’s redundancy. More than one group of replicated tasks are optimistically executed. This method has a 50-100% better throughput over NMR but does not jeopardize the fault tolerance of the basic NMR system. Unlike other methods, this technique applies to systems as small as three processors (TMR). Variations on the granularity and dependencies of tasks are considered.

Efficient implementation techniques for gracefully degradable multiprocessor systems

We propose the dynamic reconfiguration network (DRN) and a monitoring-at-transmission (MAT) bus to support dynamic reconfiguration of an N-modular redundancy multiprocessor system. In the reconfiguration process, a maximal number of processor triads are guaranteed to be formed on each processor cluster, thus supporting gracefully degradable operations. This is made possible by dynamically routing the control and clock signals of processors on the DRN so as to synchronize fault-free processors. The MAT bus is an efficient way to implement a triple modular redundant pipeline voter, which is a special case of the voting network proposed by Parhami (1991). Extensive experimental results have shown to support our design concept, and the performance of different cache memory organizations is evaluated through an analytic model.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

N-modular redundancy using the theory of error correcting codes

Using redundancy is basic to fault-tolerant computing. N-modular redundancy (NMR) is in some ways analogous to the use of a repetition code where an information symbol is replicated as parity symbols in a codeword. Linear error-correcting codes (ECC) use linear combinations of information symbols as parity symbols to generate syndromes for error patterns. In this paper, ECC theory has been applied to derive redundant circuits that tolerate faults in both the modules and checkers. Circuits using comparators for diagnosis are derived with a non-graph-theoretic approach. Coding theoretic principles are applied directly to NMR, so that extensive diagnosis of the fault-tolerant system is achieved.

Analysis of noncoherent systems and an architecture for the computation of the system reliability

An efficient technique for computing the reliability of k-to-l-out-of-n systems is presented. These kinds of systems find application in communication, multiprocessor, and transportation system environments. The k-to-l-out-of-n systems are very general and readily model coherent systems such as series, parallel, and N-modular-redundancy (NMR) systems. The algorithm presented computes in quadratic time in the worst case and yields superior results compared to existing algorithms for all permissible values of k, l, and n. The scheme is shown to evaluate the reliability in linear order-time. A cellular implementation of the algorithm in hardware is presented. The basic cell consists of a simple multiplier, an adder, and some switches that can be easily implemented in VLSI using computer-aided-design (CAD) tools. Ways of obtaining optimal configurations for the k-to-l-out-of-n system are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Mean life of k-to-l-out-of-n systems with nonidentical Weibull distribution components

A k-to-l-out-of-n system is a noncoherent system in which no fewer than k and no more than l out of n units are to function for the successful operation of the system. Examples of noncoherent systems are found in communication, multiprocessor and transportation systems. A noncoherent system is very general and includes the parallel, series and N-Modular Redundancy (NMR) systems as special cases. In this paper presents the formulas for calculating the reliability and the mean life of a k-to-l-out-of-n system with non-identical weibull distribution components.