N-channel Polycrystalline Silicon Research Articles

Electrical Characteristics of a Reduced-Gate Structure Polycrystalline Silicon Thin Film Transistor Using Field-Aided Lateral Crystallization

In order to reduce the leakage current in n-channel polycrystalline silicon thin film transistors processed by field-aided lateral crystallization, we applied a reduced gate structure that enables an offset region between the channel and source-drain. The structure in this study was much simpler than those of other methods in the sense that it could accomplish both offset-gate and Ni-offset effects simultaneously without employing any additional masks or processes. The leakage current decreased as the offset region length ΔL per side increased. When ΔL = 2 μm, which corresponded to 10 percent of the total channel length of L = 20 μm, the off-state leakage current decreased to 3.2 pA/μm at VD = 0.1 V and VG = -10 V, which is more than two orders of magnitude lower than that in the conventional structure. In addition to a reduction in leakage current, other device parameters did not change significantly.

Stress-Induced Off-Current under On- and Off-State Stress Voltages in Low-Temperature n-Channel Polycrystalline Silicon Thin-Film Transistors

The changes in off-current under on- and off-state stress voltages in n-channel polycrystalline silicon (poly-Si) thin-film transistors (TFTs) are investigated through measurements and simulations. It is found that the off-current increases markedly in the shallow-negative-gate-voltage region and decreases in the deep-gate-voltage region after applying both on- and off-state stresses, resulting in a weaker dependence on negative gate voltage. It can be supposed from the simulations and experiments that the donor-type trap states (positive charges) with a hump-type state profile, located at 0.1–0.2 eV below the midgap, and tail states are generated near the drain junction after applying both stresses. The amount of donor-type states increases in phonon-assisted tunneling with the Pool–Frenkel effect (PAT) and Schockley–Read–Hall generation (SRH) owing to the increase in the deep-trap-state density, and decreases in band-to-band tunneling (BBT) owing to the decrease in electric field, giving rise to a predominant PAT+SRH current in off-current in a wide-negative-gate-voltage region.

Hot-Carrier Effect in Polycrystalline Silicon n-Channel Lightly Doped Drain Thin-Film Transistors with Low n- Impurity Concentration

Hot-carrier effect in low-temperature n-channel polycrystalline silicon (poly-Si) lightly doped drain (LDD) thin-film transistors (TFTs) for various n- doping concentrations was examined by using a two-dimensional (2D) device simulation. It was found that, in the case of a low n- doping concentration for a high applied gate voltage, large potential drops appeared at the source side and the drain side. This was because of the reduced potential drop in the channel region, giving rise to a high lateral field and an impact ionization rate at both the source and the drain sides. These results suggested that the hot-carrier degradation due to avalanche hot-carriers occurred at both the source and the drain sides in a high-applied-gate-voltage region in the case of a low n- doping concentration, while, in the case of low gate voltage, the degradation occurred at only the high-field drain side. Therefore, the n- doping concentration should be optimized to minimize the hot-carrier degradation in the source side and the drain side.

Origin of hysteresis in current-voltage characteristics of polycrystalline silicon thin-film transistors

In this work we report the observation and characterization of a hysteresis phenomenon in the transfer characteristics of n-channel polycrystalline silicon (poly-Si) thin-film transistors (TFTs). Such phenomenon is observed in devices with fully depleted channel and not treated with hydrogen-related anneal. The origin of the hysteresis is identified to be related to the electron trapping and detrapping processes associated with the deep-level traps in the grain boundaries of the poly-Si channel.

Vertical n-Channel Poly-Si Thin-Film Transistors With Symmetric S/D Fabricated by Ni-Silicide-Induced Lateral-Crystallization Technology

We have successfully developed and fabricated the vertical n-channel polycrystalline silicon thin-film transistors with symmetric S/D fabricated by Ni-silicide-induced lateral-crystallization technology (NSILC-VTFTs). The NSILC-VTFTs are S/D symmetric devices and equivalent to dual-gate devices. The dual-gate structure of NSILC-VTFTs can moderate the lateral electrical field in the drain depletion region, significantly reducing the leakage current. In NSILC-VTFTs, the Ni accumulation and grain boundaries induced from S/D sides can be centralized in the n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> floating region. The effects of Ni accumulation in symmetric VTFTs crystallized by NSILC and metal-induced lateral crystallization are studied. In addition, a two-step lateral crystallization has been introduced to improve the crystal integrity through secondary crystallization. The NSILC-VTFTs crystallized by two-step lateral crystallization show a steep subthreshold swing of 180 mV/dec and field effect mobility mu = 553 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vmiddots without NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> plasma treatment.

Polarity Change of Threshold Voltage Shifts for n-channel Polycrystalline Silicon Thin-Film Transistors Stressed by Negative Gate Bias

The negative bias instability on p-channel and n-channel polycrystalline silicon thin-film transistor is investigated. Negative threshold voltage shift is observed in p-channel TFTs and is attributed to the positively charged donor type interface traps. On the other hand, polarity change of threshold voltage shift is observed in n-channel TFTs, suggesting two competing mechanisms. Negatively charged acceptor type interface traps are the dominant factor for the positive threshold voltage shift. As the gate stress voltage increases, accumulated holes are trapped in the insulator via Fowler-Nordheim tunneling and are responsible for the negative threshold voltage shift. The stress-induced hump effect is attributed to higher electric filed at the edge transistors as compared to channel transistor along the channel width direction.

Polarity Change of Threshold Voltage Shifts for n-channel Polycrystalline Silicon Thin-Film Transistors Stressed by Negative Gate Bias

not Available.

Hot-Carrier Degradation and Electric Field and Electron Concentration near Drain Junction in Low-Temperature N-Channel Single Drain and Lightly Doped Drain Polycrystalline Silicon Thin Film Transistors

We proposed a two-dimensional (2-D) physical model of n-channel polycrystalline silicon (poly-Si) single drain (SD) and lightly-doped drain (LDD) thin film transistor (TFT) to analyze hot-carrier degradation. The model is based on a 2-D device simulator's Gaussian doping profiles for the source and drain junctions fitted to the lateral and vertical impurity profiles in poly-Si obtained from a 2-D process simulator. It is found that, for current saturation bias, the maximum 2-D lateral electric field is located in the deep drain region under the gate, and the current flows in the deep channel region near the drain junction. In poly-Si n-channel TFTs, it was predicted from our 2-D device simulation that the generation of both band-tail states in poly-Si and interface states at both interfaces can contribute to hot-carrier degradation. We have shown that, in the case of n-channel SD TFTs, generated band-tail states greatly affect drain avalanche hot-carrier (DAHC) degradation for longer stress time of 10,000 s.

Mechanical strain effect of n-channel polycrystalline silicon thin-film transistors

The current change of n-channel polycrystalline silicon thin-film transistors is analyzed experimentally and theoretically under different strain conditions. Under the uniaxial strain parallel to the channel, the +6.7% and +5.3% drain current enhancements are achieved in linear and saturation regions, respectively. There are −4.4% (linear) and −4.6% (saturation) drain current degradations when the uniaxial strain is applied perpendicular to the channel. The polycrystalline silicon is mainly composed of (111)-oriented grains, measured by electron diffraction pattern. Phonon-limited mobility is theoretically calculated. There is a qualitative agreement between experiments and theoretical analysis.

Electrical Characteristics and Reliability of Multi-channel Polycrystalline Silicon Thin-Film Transistors

We demonstrate the fabrication process and the electrical characteristics of n-channel polycrystalline silicon thin-film transistors (poly-Si TFTs) with different numbers of channel stripes. The device's electrical characteristics, such as on-current, threshold voltage, and subthreshold swing, were improved by increasing the number of channel stripes due to the enhancement of gate control. However, the electric field strength near the drain side was enlarged in multi-channel structures, causing severe impact ionization. The degradation of device's reliability under various electrical stress conditions was suggested.

Numerical simulation of parasitic resistance effects in polycrystalline silicon TFTs

Parasitic resistance effects have been investigated in n-channel polycrystalline (polysilicon) silicon thin film transistors (TFTs). We show, both experimentally, and by using two-dimensional numerical simulations, that the transfer characteristics and, in particular, the transconductance are degraded by parasitic resistance effects, which are related to residual implant damage. In particular, we show that residual implant damage gives rise to two types of defected regions across the edges of the gate: the first, not overlapped by the gate, which mainly controls the parasitic resistance. The second, which is gate overlapped, can affect the behavior of the threshold voltage by modifying the classical short channel effect to the reverse short channel effect. The analysis demonstrates that for the fabrication of short-channel polysilicon TFTs an exact control of the implant-damaged regions is necessary.

On the Conduction Mechanism in Polycrystalline Silicon Thin-Film Transistors

Physical and electrical analyses were carried out on n-channel polycrystalline silicon thin-film transistors (nTFTs) with active regions as thin as approximately 6 nm. Such thin active regions extinguish the dominating effects of anomalous leakage and allow the conduction energy barrier height to be analyzed as a function of gate voltage in the femtoampere source/drain current regime. Grain size statistics were determined using plan view transmission electron microscopy. It is shown for the first time that in the absence of anomalous leakage, the barrier height does not decrease with decreasing gate voltage. In addition, the maximum measured barrier height is almost independent of active region thickness and grain size statistics. The source/drain current at low lateral field and high vertical field is also independent of channel length for all devices with length varied over an order of magnitude. These important discrepancies with existing TFT conduction theory are discussed within a physics-based model that addresses the effects of disorder-induced localized electron states in the bandgap. Besides describing existing data and well-known TFT behavioral trends, the model predicts a previously unknown relationship between threshold voltage variation, average threshold voltage and the number of grains in the channel. Analysis of data gathered from hundreds of devices of different dimensions across three different grain size distributions not only leads to agreement with the model but also to a remarkable universal behavior linking electrical and physical properties. This study shows the physics of polycrystalline silicon TFT conduction to be of the same form as amorphous and single crystal devices with the degree of disorder as the sliding scale between the two extremes.

Substrate current and degradation of n-channel polycrystalline silicon thin-film transistors

Experimental investigation of the substrate current I sub as a function of the gate voltage has been performed in n-channel polycrystalline silicon thin-film transistors (polysilicon TFTs), considering the drain voltage as a parameter of the study. At low gate voltages, I sub exhibits a peak located close to the threshold voltage of the transistor due to hot-carriers generated by impact ionization. At higher gate voltages, I sub increases monotonically with increasing the gate voltage, which is attributed to the temperature rise owing to self-heating. The degradation behavior of polysilicon TFTs, stressed under two different gate and drain bias conditions that cause the same substrate current due to hot-carrier and self-heating effects, is investigated.

Change in Transfer and Low-Frequency Noise Characteristics of n-Channel Polysilicon TFTs Due to Hot-Carrier Degradation

Results on the impact of hot-carrier effects on the transfer and low-frequency noise characteristics of n-channel poly-crystalline silicon thin-film transistors (polysilicon TFTs) are presented. After stressing at the condition of maximum substrate current, the experimental data show that TFTs suffer from substantial on-current reduction. Through numerical simulation, it is shown that the stress-induced degradation increases the density of the band tail traps in a region extending 200 nm from the drain and the series resistance on the drain side. It is found that the origin of the noise is reverted from carrier number fluctuation for the unstressed to the mobility fluctuation for the stressed device.

Anomalous hot-carrier-induced degradation of offset gated polycrystalline silicon thin-film transistors

Hot-carrier effects in offset gated n-channel polycrystalline silicon thin-film transistors of channel length L=10 μm and intrinsic offset lengths ΔL=0.5 and 1 μm are investigated. The gate- and drain-bias conditions for maximum device degradation were determined from substrate current measurements. The experimental data show that hot-carrier stress provokes an anomalous threshold voltage and on-state current degradation, exhibiting a “staircase-like” degradation with stress time. These results lead to the conclusion that, at the initial stages of stress, a small offset region from the drain end is damaged due to charging of the grain boundaries. As the stress proceeds further and the grain boundary traps are filled with electrons generated by impact ionization, the damage is transferred to the neighboring offset region, resulting in a staircase-like degradation of the device parameters with stress time.

Oxygen plasma and high pressure H 2 O vapor heat treatments used to fabricate polycrystalline silicon thin film transistors

Oxygen plasma and high pressure H2O vapor heat treatment were applied to fabrication of n-channel polycrystalline silicon thin film transistors (poly-Si TFTs). 13.56 MHz-oxygen-plasma treatment at 250 °C, 100 W for 5 min effectively reduced defect states of 25-nm-thick silicon films crystallized by 30 ns-pulsed XeCl excimer laser irradiation. 1.3×106-Pa-H2O vapor heat treatment at 260 °C for 3 h was carried out in order to improve electrical properties of SiOx gate insulators and SiOx/Si interfaces. A carrier mobility of 470 cm2/V s and a low threshold voltage of 1.8 V were achieved for TFTs fabricated with crystallization at 285 mJ/cm2.

Polycrystalline silicon thin-film transistors fabricated by defect reduction methods

Fabrication of n-channel polycrystalline silicon thin-film transistors (poly-Si TFTs) at a low temperature is reported. 13.56 MHz-oxygen plasma at a 100 W, 130 Pa at 250/spl deg/C for 5 min, and heat treatment at 260/spl deg/C with 1.3/spl times/10/sup 6/-Pa-H/sub 2/O vapor for 3 h were applied to reduction of the density of defect states in 25-nm-thick silicon films crystallized by irradiation of a 30 ns-pulsed XeCl excimer laser. Defect reduction was numerically analyzed. Those treatments resulted in a high carrier mobility of 830 cm/sup 2//Vs and a low threshold voltage of 1.5 V at a laser crystallization energy density of 285 mJ/cm/sup 2/.

Improved stability of short-channel hydrogenated N-channel polycrystalline silicon thin-film transistors with very thin ECR N2O-plasma gate oxide

Stability has been investigated for short-channel hydrogenated n-channel polycrystalline thin-film transistors (poly-Si TFTs) with very thin (12 nm) electron cyclotron resonance (ECR) N/sub 2/O-plasma gate oxide. The TFTs show negligible changes in the electrical characteristics after hot-carrier stresses, which is due to the highly reliable interface and gate oxide. The hydrogenated TFTs with 3-/spl mu/m gate length TFTs exhibit very small degradation (/spl Delta/V/sub th/<15 mV) under hot-carrier stresses and Fowler-Nordheim (F-N) stress (/spl Delta/V/sub th/=/sub 81/ mV, /spl Delta/Gm/Gm=2.2%, /spl Delta/S/S=4.7%).

The effects of glass-substrate’s surface-treatment on the characteristics of N-channel polycrystalline silicon thin film transistors

We have examined the performance and hot-carrier stress reliability of n-channel polycrystalline silicon (poly-Si) thin film transistors (TFTs) on RCA-leached glass. We have found out that the TFT’s performance and reliability are improved by RCA-leaching of the glass when compared to TFTs on bare glass due to the formation of a silica-rich layer on the glass surface by the RCA-leaching. The silica-rich layer acts as a barrier for impurity diffusion from glass as well as it modifies the poly-Si/glass interface which determines the physical structure of the active poly-Si.

Low-temperature and low thermal budget fabrication of polycrystalline silicon thin-film transistors

A top-gate self-aligned n-channel polycrystalline silicon (poly-Si) thin-film transistor (TFT) has been fabricated with low temperature (/spl les/550/spl deg/C) and low thermal budget process. The ultrahigh vacuum chemical vapor deposition (UHV/CVD) grown poly-Si was served as the channel film, the chemical mechanical polishing (CMP) technique was used to polish the channel surface, plasma-enhanced chemical vapor deposited (PECVD) tetraethylorthosilicate (TEOS) oxide was used as the gate dielectric, and NH/sub 3/ plasma was used to passive the device. In this process, the solid phase crystallization (SPC) step is not needed. A field effect mobility of 46 cm/sup 2//V-s, ON/OFF current ratio of over 10/sup 7/, and threshold voltage of 0.8 V are obtained. The significant reduction in process temperature and thermal budget make this process advantageous for larger-area-display peripheral driver circuits on glass substrate.