N-channel MOSFETs Research Articles

Numerical Simulation on the Impact of Back Gate Voltage in Thin Body and Thin Buried Oxide of Silicon on Insulator (SOI) MOSFETs

Silicon-on-Insulator (SOI) technology provides a solution for controlling Short-Channel Effects (SCEs) and enhancing the performance of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). However, scaling down SOI MOSFETs to a nanometer scale does not necessarily yield further scaling benefits. Introducing multiple gates, such as a double gate configuration, can effectively mitigate SCEs. Nonetheless, fabricating a flawless double gate structure is an exceedingly challenging endeavor that remains unrealized. The adoption of a back gate bias, with an asymmetrical thickness arrangement between the front and back gates, mimicking the behavior of a double gate, offers an alternative approach. This approach has the potential to modify the electrical characteristics of the device, thus potentially leading to improved control over SCEs. In this study, we employed 2D simulations using Atlas to investigate the influence of back gate biases, namely, -2.0 V, 0 V, and 2.0 V on a 10 nm silicon thickness at the top and a 20 nm buried oxide thickness for n-channel MOSFETs. We focused on key parameters, including threshold voltage (VTh), Drain Induced Barrier Lowering (DIBL), and Subthreshold Swing (SS). The results demonstrate that a negative back gate bias is the most favorable configuration, as it yields superior performance. This translates into more effectively controlled SCEs across all the parameters of interest.

Demonstration of SiC n-channel MOSFETs fabricated on a high-purity semi-insulating substrate and investigation of the short-channel effects

N-channel MOSFETs fabricated on a high-purity semi-insulating (HPSI) 4H-SiC substrate were demonstrated. The fabricated MOSFETs exhibited normally-off transistor operation and the peak field effect mobility (μ FE,peak) was 30 cm2 V−1 s−1, which was lower than that of the p−-body MOSFETs (N A = 2 × 1015 cm−3). The critical channel length (L crit) was 1.48 μm for the HPSI MOSFETs, which was shorter than that for the p−-body MOSFETs. In the HPSI MOSFETs, electrons trapped by the compensating defects in the HPSI substrate increase as the Fermi level moves up, which may be the main cause for the resulting low μ FE,peak and short L crit.

Enhanced Detection of Klebsiella Pneumoniae Using Electric-Double-Layer FET Sensor: Rapid, Temperature-Boosted Probe-Target Binding Analysis

Klebsiella pneumoniae demonstrates versatility in its pathogenicity, leading to diverse infections in humans such as pneumonia, urinary tract infections, bacteremia, wound infections, meningitis, endocarditis, and sepsis. The severity of these infections is contingent upon the patient's immune status, the site of infection, and the existence of underlying medical comorbidities. A sputum or urine culture, on the other hand, typically takes between 24 and 72 hours to produce results. Over recent years, various innovative methodologies have emerged, including optical and electrochemical techniques and molecular detection via PCR. Despite the diversity of available techniques, concerns persist regarding their sensitivity and specificity. Moreover, fluorescence-based methodologies and Surface Plasmon Resonance (SPR)-based sensors have been explored for bacterial detection. However, these existing methods have drawbacks such as elevated costs, prolonged turnaround times, the need for sophisticated instrumentation, and a demand for skilled personnel. Field-effect transistor (FET) sensors have garnered considerable scientific attention since their inception due to their remarkable sensitivity, facile signal readout, and the capability for label-free assays. The aim of this research is to detect the detect Klebsiella pneumoniae bacteria in blood serum by double electric layer (EDL) extended-gate field-effect transistor (FET) sensor. In this study, a preliminary investigation employed a single-step surface functionalization approach to immobilize receptor probes, specifically single-stranded DNA (ssDNA). This strategy aimed to enable the rapid detection of complementary DNA (cDNA) across varying concentrations, leveraging differential gate voltages to modulate the sensitivity of this analytical platform. The designed probes were successfully immobilized onto a disposable chip housing a pair of gold electrodes. A handheld reader, integrating enhancement-mode N-channel MOSFETs, established connectivity with a laptop via a USB port to facilitate the measurement of sensor signals. By applying pulsed gate voltage to the input electrode, which modulates the channel conductivity which behaves as a function of the charge distribution within the EDL structure, consequently influencing the drain current of the MOSFET. The immobilized probe, positioned on the gate electrode, underwent testing using varying concentrations of cDNA introduced into TE buffer. Detection of probe-target binding occurred through fluorescence alterations and electrically by assessing changes in drain current. In order to improve the response time, we elevated the temperature near the Tm enhances sensitivity and binding rates, in shorter time period of 1 minutes. Figure 1

An investigation of 60Co gamma radiation induced damage in N-channel MOSFETS at cryogenic temperature.

N-channel depletion metal oxide semiconductor field effect transistors (MOSFETs) were irradiated with 60Co gamma radiation in the dose range of 100 krad to 6Mrad at cryogenic (77K) and room temperatures (300K). The MOS devices irradiated at 77K and 300K were characterized at 77K and 300K respectively. The different electrical parameters of MOSFET such as threshold voltage (Vth), density of interface trapped charges (ΔNit), density of oxide trapped charges (ΔNot) and mobility of the charge carriers (μ) were studied as a function of total dose. A considerable increase in ΔNit and ΔNot and decrease in Vth was observed after irradiation. The 77K irradiation results were then compared with 300K irradiation results and found that the degradation in the electrical characteristics is more for the devices irradiated at 300K.

Dynamic Performance Evaluation of N-channel MOSFET under Gamma Irradiation

Dynamic Performance Evaluation of N-channel MOSFET under Gamma Irradiation

Combined Fabrication and Performance Evaluation of TOPCon Back‐Contact Solar Cells with Lateral Power Metal‐Oxide‐Semiconductor Field‐Effect Transistors on a Single Substrate

Nowadays, an increasing share of photovoltaic (PV) systems makes use of module‐ or submodule‐level power electronics (PE). Furthermore, PE is used in stand‐alone devices powered by PV‐storage solutions. One way to facilitate further implementation of PE in PV applications is to integrate PE components into crystalline silicon PV cells. Herein, the COSMOS device is introduced, denoting COmbined Solar cell and metal‐oxide‐semiconductor field‐effect transistor (MOSFET). Specifically, the combined manufacturing of lateral power MOSFETs and interdigitated back contact solar cells with tunnel‐oxide passivated contacts (TOPCon) on a single wafer is reported. Many steps of the proposed process flow are used for the fabrication of both devices, enabling cost‐effective integration of the MOSFET. Both n‐type solar cells with integrated p‐channel MOSFETs (PMOS) and p‐type solar cells with integrated n‐channel MOSFETs (NMOS) are successfully manufactured. NMOS devices perform better in achieving low on‐resistance, while PMOS devices exhibit lower leakage currents. Furthermore, the study reveals integration challenges where off‐state leakage currents of the MOSFET can increase due to illumination and specific configurations of monolithic interconnections between the MOSFET and the solar cell. Nevertheless, for both n‐type and p‐type solar cells, efficiencies exceeding 20% are achieved, highlighting the potential of the proposed process for COSMOS devices.

N-Channel MOSFET Reliability Issue Induced by Visible/Near-Infrared Photons in Image Sensors

Image sensors such as single-photon avalanched diode (SPAD) arrays typically adopt in-pixel quenching and readout circuits, and the under-illumination first-stage readout circuits often employs high-threshold input/output (I/O) or thick-oxide metal-oxide-semiconductor field-effect transistors (MOSFETs). We have observed reliability issues with high-threshold n-channel MOSFETs when they are exposed to strong visible light. The specific stress conditions have been applied to observe the drain current (Id) variations as a function of gate voltage. The experimental results indicate that photo-induced hot electrons generate interface trap states, leading to Id degradation including increased off-state current (Ioff) and decreased on-state current (Ion). The increased Ioff further activates parasitic bipolar junction transistors (BJT). This reliability issue can be avoided by forming an inversion layer in the channel under appropriate bias conditions or by reducing the incident photon energy.

Semi-classical Monte Carlo study of the impact of tensile strain on the performance limits of monolayer MoS2 n-channel MOSFETs

The effects of tensile strain and contact transmissivity on the performance limits of monolayer molybdenum disulfide (MoS2) nanoscale n-channel MOSFETs are studied using a semi-classical Monte Carlo method. Density functional theory calculations were performed to parametrize the electronic band structure of MoS2 subject to tensile and shear strain. Tensile strain decreases the bandgap, increases the inter-valley band-edge energy separation between the light-mass K-valleys and heavier-mass Q-valleys, and decreases the K-valley effective mass in a way that depends on the direction and the amount of the applied strain. Biaxial tensile strain and uniaxial tensile strain along the x- or y-directions are found to have the largest effect. In bulk materials, low-field phonon-limited electron mobility is enhanced, peak and saturation drift velocities are increased, and high-field negative differential resistance becomes more pronounced. Both 200 and 15 nm gate length MoS2 MOSFETs with end-contacts with ideal (unity) and more realistic (significantly sub-unity) contact interface transmissivity were simulated. These MoS2 devices exhibited substantial sensitivity to strain with ideal contact transmissivity, and more so for the 15 nm quasi-ballistic device scale than 200 nm long-channel devices. However, the results showed much less strain sensitivity for devices with more realistic contact transmissivities, which may be good or bad depending on whether strain-insensitive or strain-sensitive performance is desired for a particular application and may be possible to modify with improved contact geometries.

Different temperature dependence of mobility in n- and p-channel 4H-SiC MOSFETs

The impact of interface state density (D it) near the conduction band edge (E C) and the VB edge (E V) on the field-effect mobility (μ FE) of NO- and N2-annealed n- and p-channel MOSFETs was investigated. With lowering the temperature, μ FE of n-channel MOSFETs decreased whereas μ FE increased in p-channel devices. Despite the comparable D it values near E C and E V, p-channel MOSFETs have less trapped carriers due to a deeper surface Fermi level caused by the larger effective masses of holes, resulting in smaller Coulomb scattering, and this may cause the different temperature dependence of μ FE in n- and p-channel MOSFETs.

Design on Formation of Nickel Silicide by a Low‐Temperature Pulsed Laser Annealing Method to Reduce Contact Resistance for CMOS Inverter and 6T‐SRAM on a Wafer‐Scale Flexible Substrate

AbstractA pulsed laser annealing method is utilized to directly synthesize nickel silicide (NiSi) as a contact material to improve the contact of electric devices. Three laser wavelengths, 355 nm (ultraviolet laser), 532 nm (green laser), and 1064 nm (infrared laser), are used for the NiSi synthesis during the pulsed laser annealing process. A NiSi phase with low sheet resistance is formed by an ultraviolet laser annealing (ULA) process without damaging the polyimide (PI) substrate. With the integration of the ULA process‐induced NiSi into p‐nnel MOSFET (PMOS) and n‐channel MOSFET (NMOS) devices, the on/off ratio improves significantly, and the field‐effect mobility increases by 30% because of the reduction in contact resistance from 21 to 8.5 kΩ. In addition to the PMOS and NMOS, the gains of the CMOS inverter at different Vdd values are improved by at least 30%. Moreover, the static noise margin of 6T‐SRAM is elevated from 0.82 to 1 V at Vdd = 4 V. The ability of the ULA process to synthesize a high‐quality NiSi layer on a flexible substrate is demonstrated. The integration of NiSi into electrical devices offers a new pathway for improving the electrical behavior of flexible devices.

Rapid and Sensitive Pathogen Detection in Serum for Early Sepsis Diagnostics Using an Electrical-Double-Layer Gated Field-Effect Transistor-Based Sensor Array

Sepsis is a major medical inflammatory response to bloodstream infection caused bypathogens. Over 30 million infections occur due to sepsis in a year throughout the globe.With over 6 million deaths, sepsis treatment demands timely diagnosis and medicalinterventions to prevent large outspread of the infection. Rapid and sensitive detection ofinfectious bacteria plays an important role in disease control. However, fast and accuratediagnosis remains highly challenging for many hospitalized patients. Among variousbacterial diseases, Escherichia coli, (E. coli) a gram-negative bacterium, is the mostfrequently and extensively researched and has become a global concern of food safetyproblems. Traditional cell culture methods are considered as most accurate method forbacterial diagnosis. But some microorganisms like Bartonella spp, Treponema pallidum, etc.are difficult to grow on a culture plate, while some other virus species are unculturable, soeventually the traditional cell culture may take several days to a week for the diagnosticresults. Hence, over several years, different novel methods have been developed, such asoptical methods, electrochemical methods, molecular detection by PCR etc. Even thoughseveral techniques exist, concerns have been raised regarding their sensitivity, specificity etc.In addition, various fluorescence-based methods, and Surface Plasmon resonance (SPR)-based sensors have also been reported for bacterial detection. However, high cost, largeturnaround time, expensive instrumentation, and requirement of skilled personnel are some ofthe disadvantages of these existing techniques.FET biosensors have previously been used in different diagnosis areas. Nowadays, severalFET-based biosensors have been developed, which primarily concentrate on improving theoverall sensitivity of FET devices. However, the charge screening effect observed in aphysiological environment, and additional sample processing increase the complexity of thesensor platform. To overcome this hurdle, an electrical double layer (EDL) gated FETbiosensor has been proposed and explored in the detection of a variety of biological entities.Here, we proposed an EDL-FET sensor platform for the detection of Escherichia coliO157:H7 strain in blood serum. A single-step surface functionalization strategy was used forimmobilizing receptor probes as ssDNA. The probes were designed and immobilized over adisposable chip containing a pair of gold electrodes. A handheld reader which consists of anenhancement mode N-channel MOSFETs was connected to the laptop through a USB port tomeasure the sensor signals. Pulsed gate voltage was applied to the input electrode and whichmodulated the EDL capacitance and potential change eventually resulting in the drain currentof the MOSFET. The probe was immobilized on the gate electrode and tested with differentconcentrations of cDNA spiked in TE buffer. The probe-target binding was observed throughfluorescence change and electrically by measuring the change in drain current. In addition,surface potential change was also examined by performing KPFM test. Similarly, the BioFETdetections were validated for E. coli O157 variants by spiking with short and long DNAtarget sequences simultaneously in serum. The test results confirm selectivity by testingvarious non-complementary sequences, which ensures the potential of this BioFET as apoint-of-care sensing device. Figure 1

In vestigation the Impact of Silicon Film Thickness on FDSOI and PDSOI MOSFET Characteristics

The performance of chip is degraded because of the short-channel effect (SCE) as the metal oxide semiconductor field effect transistor (MOSFET) size scales down. Silicon on insulator (SOI) technology helps to reduce the short channel effects and permits a good solution to the miniaturization. The electrical characteristics of fully depleted SOI (FDSOI) and partially depleted SOI (PDSOI) n-channel MOSFET (N-MOSFET) are investigated as silicon film thickness is varied in this paper. Both transistors are compared in terms of electrical parameters which are the threshold voltage, subthreshold slope, on-state current, leakage current and drain induced barrier lowering (DIBL). Silvaco TCAD tools are used for simulating both PDSOI and FDSOI MOSFETs. FDSOI MOSFET is superior to PDSOI MOSFET based on found simulation results.

Interpretation of mobility universality against effective electric field of Si nMOSFETs based on nonlinear model of surface roughness scattering

The universality of mobility against the effective electric field of Si n-channel MOSFETs (nMOSFETs) is not guaranteed under the nonlinear model of surface roughness scattering, which has been recently proposed and is more quantitative than the conventional linear model. Therefore, in this study, the mechanism of the universality of the mobility is quantitatively examined for (100) and (110) Si nMOSFETs based on the nonlinear model. As a result, the coefficient in the effective field to provide the universality is theoretically shown to be 1/2 and 1/3 for (100) and (110) Si nMOSFETs, respectively, and the physical origin is addressed.

Field Effect Transistor with Nanoporous Gold Electrode.

Nanoporous gold (NPG) has excellent catalytic activity and has been used in the recent literature on this issue as a sensor in various electrochemical and bioelectrochemical reactions. This paper reports on a new type of metal-oxide-semiconductor field-effect transistor (MOSFET) that utilizes NPG as a gate electrode. Both n-channel and p-channel MOSFETs with NPG gate electrodes have been fabricated. The MOSFETs can be used as sensors and the results of two experiments are reported: the detection of glucose and the detection of carbon monoxide. A detailed comparison of the performance of the new MOSFET to that of the older generation of MOSFETs fitted with zinc oxide gate electrodes is given.

Investigation of Incident Angle Dependence of Single Event Transient Model in MOSFET

As the manufacturing process level of semiconductor devices continues to improve, the device size gradually decreases, and the devices are affected by the single event effect more and more severely. In this paper, the physical process of single particle incident N-channel Metal-Oxide-Semiconductor Field-Effect Transistor (NMOSFET) is simulated. By changing the particle incidence position, incidence angle, LET value, and temperature, the transient current variation with time is obtained, and the susceptibility of the device to single event effect under the action of four factors is analyzed, which provides the basis for the next research of the device against single event effect and ideas for the radiation hardening of semiconductor devices. In addition, in these experiments, there were bimodal-shaped current pulses that were different from single peak transient current pulses. Therefore, a new model describing the bimodal single event transient (SET) current waveform was proposed, which can be used as a current source model in circuit simulation and help to predict the ability of the circuit to resist the single event effect.

The effect of gate geometric effect and polysilicon doping on the performance of scaled NMOS

Insufficiently high doping in polysilicon gates of metal oxide semiconductor field effect transistor (MOSFET) becomes unavoidable due to the demands for low-energy ion implantation and limited annealing conditions to achieve ultra-shallow source and drain junctions. This results in the poly-depletion effect for ultra-thin MOSFET, loss of current drive and shift in the threshold voltage. This problem gets intense when the device is further scaled down for the gate length and thickness of gate oxide. Hence, our current work focuses on the effect of gate geometrical effect and polysilicon gate doping on scaled n-channel MOSFET(NMOS) performance. The NMOS device was constructed using TCAD ATLAS tools from SILVACO software. Six different gate lengths of 0.6 μm, 0.4 μm, 0.2 μm, 60 nm, 40 nm and 20 nm were set, and the n-type doping concentration in the polysilicon gate was varied to 1× 1018, 1× 1020 and 1 × 1021 cm-3 respectively to see their effect on the NMOS I-V and C-V performances. The findings showed that as the gate length is scaled down, the drain current increases, and as the concentration of the polysilicon doping increases, the value of the threshold voltage, VTH decreases. Based on the simulation and data collected, it can be concluded that the optimum concentration of polysilicon doping that can reduce the poly-depletion effect is 1 × 1021 cm-3, and the optimum gate length that can be used to overcome the problem is 20 nm.

Substrate noise evaluation for lightly doped 45nm N-MOSFET using physical simulation models

ABSTRACT Analyzing substrate noise for an n-channel MOSFET (NMOS) substrate has been developed using various concepts such as virtual separation concept, p-contact to p-contact model and transistor switching noise model. A design is necessary for the substrate design development to minimize noise in FoMs (Figure Of Merits) and reduce threshold voltage developed noise. In the proposed model, a substrate-induced chip used for finding the noise in drain current has been improved with the increased doping density of an NMOS device. From a substrate noise coupling network with the proposed low signal equivalent circuit, the system measures noise at NMOS substrate using a hot carrier injection model. The proposed concept has been implemented in TCAD-SILVACO software, the design was made in ATHENA, and its corresponding electrical characteristics are simulated by the ATLAS software tool. This model extracts parameters such as overall noise in FoMs, drain current-gate current bias analysis, cross-correlation, and minimized threshold value. After capacitive coupling is achieved over different operation conditions and dimensions, excellent output is from simulated noise data.

Capacitor-Less Low-Power Neuron Circuit with Multi-Gate Feedback Field Effect Transistor

Recently, research on artificial neuron circuits imitating biological systems has been actively studied. The neuron circuit can implement an artificial neural network (ANN) capable of low-power parallel processing by configuring a biological neural network system in hardware. Conventional CMOS analog neuron circuits require many MOSFETs and membrane capacitors. Additionally, it has low energy efficiency in the first inverter stage connected to the capacitor. In this paper, we propose a low-power neuron circuit with a multi-gate feedback field effect transistor (FBFET) that can perform integration without a capacitor to solve the problem of an analog neuron circuit. The multi-gate FBFET has a low off-current due to its low operating voltage and excellent sub-threshold characteristics. We replace the n-channel MOSFET of the inverter with FBFET to suppress leakage current. FBFET devices and neuron circuits were analyzed using TACD and SPICE mixed-mode simulation. As a result, we found that the neuron circuit with multi-gate FBFET has a low subthreshold slope and can completely suppress energy consumption. We also verified the temporal and spatial integration of neuron circuits.

Influence of substrate impurity concentration on sub-threshold swing of Si n-channel MOSFETs at cryogenic temperatures down to 4 K

The sub-threshold swing (SS) of Si n-MOSFETs is experimentally and systematically evaluated in a temperature range of 4–300 K with varying the substrate impurity concentration (N sub) from ~1016 to ~1018 cm−3, to obtain a physical understanding of SS at cryogenic temperatures. It is clarified that the temperature and drain current dependencies of SS in n-MOSFETs are well represented by a model composed of mobile tail states and localized interface states, irrespective of N sub. The densities of these states are found to increase with increasing N sub. A physical origin of band tail states is studied by experimentally examining the impact of substrate bias on these states, which can separate the effects of the N sub and the surface electric field. It has been clarified, as a result, that the band tail states can be explained by the impurity-induced model.

Design of Spaceborne Stepper Motor Driver Based on FPGA

In order to meet the specific application requirements of stepper motor in space optical remote sensor, such as large load current, low operating frequency, sufficient safety margin, anti radiation and other space environment indicators, a spaceborne stepper motor driver based on antifuse Field Programmable Gate Array (FPGA) is designed. The driver consists of power conversion module, control module, drive module, and position detection module. Using P-channel Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and N-channel MOSFET to design bipolar drive circuit, the driver hardware circuit is simple and the software resource occupancy rate is low. Through the experiments of the dual functions of logic protection circuit in hardware and dead zone protection in software, it is verified that the design of spaceborne stepper motor driver based on FPGA meets the requirements of space optical remote sensor mechanism control.