N-bit Parallel Research Articles

Hardware Implementation of Parallel adder/ Subtractor and Complex Multiplier using Xilinx IP-Core

The paper aims to target the Xilinx intellectual property (IP) cores and the methodology that allows in the easy way of implementing the IP cores and its functionalities and the interface with the recent Xilinx FPGA’s. The proposed work is developed with Xilinx ISE 14.7 programming and the IP cores associated with it. VHDL programming style is used to describe the hardware and its functionality. Complex multiplier and N-bit parallel adder/subtrator is designed using Xilinx IP core approach and implemented using Virtex-5 XC5VXT50T device.

Prediction of Solutions of Arithmetic and Logical Operations on the Basis of the Mathematical Model of Cognitive Digital Automata

An approach to the problem of solution prediction of arithmetic and logical operations on the basis of the mathematical model of cognitive digital automata (CDA) is proposed. A particular advantage of the proposed approach is that the training procedure can be performed on limited (minimum) training sets. Prediction or generation of solutions is performed on the basis of the mathematical model of CDA which is formed in the course of training. As a testbed for the approach, the modeling of an n-bit parallel adder was implemented. The mathematical model of the adder was formed, which made it possible to reproduce the entire truth table for the n-bit parallel adder. The results obtained could be useful as an alternative solution to a number of problems known for conventional feed-forward neural networks, e.g. on-the-fly learning and catastrophic forgetting.

Design and analysis of low-power and area efficient N-bit parallel binary comparator

This paper presents a new low-power and area-efficient parallel binary comparator design based on prefix tree structure. Due to its wide usage in central processing units, optimizing binary comparator for low power applications are need of the hour. A novel EX-OR–NOR gate is used in proposed binary comparator as pre-encoder to reduce area, power and delay. The simulation results performed using CADENCE for CMOS 180nm—technology. The paper proposes two binary comparator architectures with improved performance. The proposed architecture result in a power reduction upto $$25\%$$ , area (number of transistors) reduces upto $$36\%$$ and improves the delay performance $$27\%$$ compared to existing technique.

FPGA Based Systolic Array for Modular Multiplication Using Precomputed Addition Value

본 논문에서는 몽고메리 알고리듬을 기반으로 하여 고속 모듈러 곱셈을 위한 새로운 시스톨릭 VLSI 알고리듬을 제안하고, 미리 계산된 덧셈 값을 이용한 FPGA에 기반한 시스톨릭 어레이를 하드웨어로 구현한다. 제안한 알고리듬에서 이 덧셈 값은 CLA 방식의 직렬 체인으로 구성된 n-bit 병렬 가산기를 사용하여 얻게 된다. 모듈러 곱셈의 계산 속도를 증가시키기 위해서 두 개의 기본 셀 (PE_X와 PE_Y)을 설계하여 시스톨릭 어레이를 구현한다. 구현 결과를 통하여 제안한 셀 PE_Y와 시스톨릭 어레이에 대한 기존의 방법과의 비교에서 셀 수는 각각 약 43%와 5% 정도 감소하였고, 임계 경로도 각각 11%와 12% 정도 감소함을 보였다.

Molecular solutions for the subset-sum problem on DNA-based supercomputing

In this paper our main purpose is to give molecular solutions for the subset-sum problem. In order to achieve this, we propose a DNA-based algorithm of an n-bit parallel adder and a DNA-based algorithm of an n-bit parallel comparator to formally verify our designed molecular solutions for the subset-sum problem.

A 200-MHz complex number multiplier using redundant binary arithmetic

Modern digital communication systems rely heavily on baseband signal processing for in-phase and quadrature (I-Q) channels, and complex number processing in low-voltage CMOS has become a necessity for channel equalization, timing recovery, modulation, and demodulation. In this work, redundant binary (RB) arithmetic is applied to complex number multiplication for the first time so that an N-bit parallel complex number multiplier can be reduced to two RE multiplications (i.e., an addition of N RB partial products) corresponding to real and imaginary parts, respectively. This efficient RE encoding scheme proposed can generate RB partial products with no additional hardware and delay overheads. A prototype 8-bit complex number multiplier containing 11.5 K transistors is integrated on 1.05/spl times/1.33 mm/sup 2/ using 0.8 /spl mu/m CMOS. The chip consumes 90 mW with 2.5 V supply when clocked at 200 MHz.

Fully parallel arithmetic algorithm for an N-bit parallel adder and its optical implementations

A fully parallel arithmetic algorithm is proposed for adding multiple numbers of any radix, in which linear operations and nonlinear operations are completely separated. The algorithm can be implemented using an optical one-stage system with shifting, weighting, summing, and thresholding functions, in favor of fully utilizing the parallelism of optics. A carry ripple propagating method and a carry look-ahead method are suggested for adding longer numbers. Three kinds of optical systems, which use respectively a cylindrical lens, a lens-array, and pairs of parallel partial reflectors, are designed for optical implementation. In particular, the system based on parallel partial reflectors can be packaged into a planar optical device. Furthermore, in this system neither the encoding nor the decoding of data is necessary and the results can be directly used for following processing.

Butterfly interconnection implementation for an n-bit parallel full adder/subtractor

Free-space optical interconnections are important in both massive digital optical computing and communication systems. The architectural features of three interconnection networks are analyzed and compared, and the optical butterfly interconnection is shown to have many advantages over other interconnections in implementing various basic logic functions such as addition, subtraction, multiplication, and fast Fourier transforms (FFTs). Starting with conventional Karnaugh maps and Boolean algebra, the characteristics of full addition and full subtraction are analyzed and compared. An n-bit parallel calculator that can implement both ripple carry full additions and ripple borrow full subtractions using multilayer butterfly interconnection networks is designed. Then the schematic and architecture of the full adder/subtractor, interconnection networks, and the patterns of key devices such as masks to implement AND and OR operations in this calculation are described in detail. The correct simulation results of several groups of multibit digits are provided. Finally, the development of the interconnections in implementing logic operations is discussed.

Butterfly interconnection implementation for an n-bit parallel ripple carry full adder

Free-space optical interconnections are important both in massive digital optical computing and in communication systems. The optical butterfly interconnection has many advantages over other interconnections in implementing various basic logic functions such as addition, subtraction, multiplication. This paper starts with the conventional Karnaugh maps and Boolean algebra to implement a parallel n-bit ripple carry full adder by the use of multilayer butterfly interconnection networks. Then we describe in detail the design and architecture of the full adder and provide accurate interconnection networks and the structures or patterns of key devices such as the masks to implement AND and OR operations in this calculation. Finally, we discuss development of the interconnection in implementing logic operations.

Parallel Binary Adders with a Minimum Number of Connections

An n-bit parallel binary adder consisting of NOR gates only in single-rail input logic is proved to require at least 17n + 1 connections for any value of n. Such an adder is proved to require at least 7n + 2 gates. An adder that attains these minimal values is shown. Also, it is concluded that some of the parallel adders with the minimum number of NOR gates derived by Lai and Muroga have the minimum number of connections as well as the minimum number of gates, except for the two modules for the two least significant bit positions.

Optical logic gates using liquid crystal light valve: implementation and application example

In this paper, we propose a new method of optically implementing digital logic gates capable of performing all logic operations and give the technique for construction of an array of n-bit parallel adders as a typical application circuit. These gates are implemented using a Hughes liquid crystal light valve operated in the parallel off-state configuration. It is found that all possible functions of two binary variables are realizable with these gates, some as bright-true-logic and some as dark-true-logic. Experimental results will be given using the portions of a single liquid crystal light valve demonstrating the feasibility of AND, NOR, XOR, etc. gate arrays. As an example of implementation of combinatorial circuits, a design for an array of binary adders will also be given.

Application of Gunn effect to subnanosecond full adder and full subtractor

An n-bit parallel full adder and a full subtractor employing Gnnn-effect devices are proposed. The important feature is a high-speed carry generator utilizing transverse spreading of high field domains, whose operation is confirmed by computer study. The delay time of these circuits will be reduced to several hundred picoseconds.