Hardware Implementation of Parallel adder/ Subtractor and Complex Multiplier using Xilinx IP-Core

Abstract

The paper aims to target the Xilinx intellectual property (IP) cores and the methodology that allows in the easy way of implementing the IP cores and its functionalities and the interface with the recent Xilinx FPGA’s. The proposed work is developed with Xilinx ISE 14.7 programming and the IP cores associated with it. VHDL programming style is used to describe the hardware and its functionality. Complex multiplier and N-bit parallel adder/subtrator is designed using Xilinx IP core approach and implemented using Virtex-5 XC5VXT50T device.