mV Supply Voltage Research Articles

Supply Voltage Dependency on the Single Event Upset Susceptibility of Temporal Dual-Feedback Flip-Flops in a 90 nm Bulk CMOS Process

In this paper we investigate the efficiency of using temporal and spatial hardening techniques in flip-flop design for single event upset (SEU) mitigation at different supply voltages. We present three novel SEU tolerant flip-flop topologies intended for low supply voltage operation. The most SEU tolerant flip-flop among the proposed flip-flop topologies shows ability of achieving maximum SEU cross-section below $1.9 \cdot 10^{-10}~\hbox{cm}^{2} /\hbox{bit}$ (no SEUs detected) at 500 mV supply voltage, $4 \cdot 10^{-10}~\hbox{cm}^{2} /\hbox{bit}$ at 250 mV supply voltage, and $2 \cdot 10^{- 9}~\hbox{cm}^{2} /\hbox{bit}$ at 180 mV supply voltage. When scaling the supply voltage from 1 V down to 500 mV, 250 mV and 180 mV, the proposed flip-flops achieve at least $ - 72\% $ , $ - 92.5\% $ and $ - 95\% $ (respectively) reduction in energy per transition compared to a Dual Interlocked Storage Cell based flip-flop when operated at a supply voltage of 1 V. The flip-flops have been designed and fabricated in a low-power commercial 90-nm bulk CMOS process and were tested using heavy ions with LET between $8.6 ~\hbox{MeV-cm}^{2} /\hbox{mg}$ and $53.7 ~\hbox{MeV-cm}^{2} /\hbox{mg}$ .

Design of Low Voltage Tunneling-FET Logic Circuits Considering Asymmetric Conduction Characteristics

Tunnel field-effect transistor (TFET) digital circuits present the opportunity for energy efficient logic operation at low voltage due to the TFET's steep subthreshold slope (SS) At a 400 mV supply voltage, TFET circuits have 4X higher performance than MOSFET circuits with process variation considered. Additional circuit operation effects arise because TFETs have asymmetric source-drain conduction. The N-TFET (P-TFET) has low conduction with negative (positive) V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> bias. As shown for the first time, this asymmetric conduction can be the cause of potential circuit failures and reliability risks if not properly avoided. It is revealed that relatively large voltages can be bootstrapped within digital TFET circuits. These bootstrapped voltages are dependent on the ratio of fixed capacitance to coupling capacitance times V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> . The bootstrapped voltages may exceed 2*V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> , but TFET's lower supply voltage (e.g., V) may mitigate reliability concerns. Circuit checks and redesign are proposed to avoid these problems. This bootstrapping phenomenon is unique to TFETs and may have significant speed and reliability impacts. A second, and favorable, aspect of TFET's asymmetric source-drain conduction is that it enables compact implementations of MUX gates. Separate pull-up and pull-down networks may be shared without concern for short circuit currents only present in MOSFETs with bi-directional conduction. Circuit considerations of TFET's asymmetric conduction are considered in detail.

A 300 mV sub-threshold region 2.4 GHz voltage-controlled oscillator and frequency divider with transformer technique for ultralow power RF applications

A new ultralow voltage 2.4 GHz voltage-controlled oscillator (VCO) and a divide-by-2 frequency divider circuits operating in a CMOS sub-threshold region using a transformer technique have been developed. In the sub-threshold region, the CMOS transistor high frequency performances are decreased to the point where oscillation and frequency division are challenging to achieve. The new proposed VCO uses the transformer feedback complementary VCO technique to improves VCO negative feedback gain. The circuits have been fabricated in a 65 nm standard CMOS process. The oscillation frequency is designed at 2.4 GHz under a 300 mV supply voltage. The total power consumption is 202 µW with noise performance of −96 dBc/Hz at 1 MHz offset. The new proposed frequency divider circuit consists of two stages master-slave D-type flip-flop (DFF). The DFF differential input is coupled to a transformer circuit instead of transistors to reduce the number of stacks. The minimum operating supply voltage is 300 mV with power consumption of 34 µW with a free-run frequency of 1.085 GHz.

A 200 mV low leakage current subthreshold SRAM bitcell in a 130 nm CMOS process

A low leakage current subthreshold SRAM in 130 nm CMOS technology is proposed for ultra low voltage (200 mV) applications. Almost all of the previous subthreshold works ignore the leakage current in both active and standby modes. To minimize leakage, a self-adaptive leakage cut off scheme is adopted in the proposed design without any extra dynamic energy dissipation or performance penalty. Combined with buffering circuit and reconfigurable operation, the proposed design ensures both read and standby stability without deteriorating writability in the subthreshold region. Compared to the referenced subthreshold SRAM bitcell, the proposed bitcell shows: (1) a better critical state noise margin, and (2) smaller leakage current in both active and standby modes. Measurement results show that the proposed SRAM functions well at a 200 mV supply voltage with 0.13 μW power consumption at 138 kHz frequency.

Ultra-low voltage implicit multiplexed differential flip-flop with enhanced noise immunity

An ultra-low voltage 22T implicit multiplexed differential (IMD) flip-flop (FF) is proposed. An implicit multiplexer is designed to simplify the differential FF complexity, while its control data path is able to enhance the FF noise immunity as well. So, the fully static IMD-FF with modified differential topology provides a sufficient noise margin under voltage scaling. On the other hand, the IMD-FF operation avoids considerable DC current dissipation to save active power and suppresses the idle leakage by stacked transistors. The post-layout simulation in 90 nm CMOS process with 400 mV supply voltage shows that the IMD-FF achieves 56% active power and 42.2% leakage power reduction. The tolerable noise energy is enhanced by 18.9% on average. Finally, this work provides 93% function yield rate under the effect of process-voltage-temperature variations and 40 pJ input noise energy.

The design and hardware implementation of a low-power real-time seizure detection algorithm

Epilepsy affects more than 1% of the world's population. Responsive neurostimulation is emerging as an alternative therapy for the 30% of the epileptic patient population that does not benefit from pharmacological treatment. Efficient seizure detection algorithms will enable closed-loop epilepsy prostheses by stimulating the epileptogenic focus within an early onset window. Critically, this is expected to reduce neuronal desensitization over time and lead to longer-term device efficacy. This work presents a novel event-based seizure detection algorithm along with a low-power digital circuit implementation. Hippocampal depth-electrode recordings from six kainate-treated rats are used to validate the algorithm and hardware performance in this preliminary study. The design process illustrates crucial trade-offs in translating mathematical models into hardware implementations and validates statistical optimizations made with empirical data analyses on results obtained using a real-time functioning hardware prototype. Using quantitatively predicted thresholds from the depth-electrode recordings, the auto-updating algorithm performs with an average sensitivity and selectivity of 95.3 ± 0.02% and 88.9 ± 0.01% (mean ± SEα = 0.05), respectively, on untrained data with a detection delay of 8.5 s [5.97, 11.04] from electrographic onset. The hardware implementation is shown feasible using CMOS circuits consuming under 350 nW of power from a 250 mV supply voltage from simulations on the MIT 180 nm SOI process.

Energy-Efficient Subthreshold Processor Design

Subthreshold circuits have drawn a strong interest in recent ultralow power research. In this paper, we present a highly efficient subthreshold microprocessor targeting sensor application. It is optimized across different design stages including ISA definition, microarchitecture evaluation and circuit and implementation optimization. Our investigation concludes that microarchitectural decisions in the subthreshold regime differ significantly from that in conventional superthreshold mode. We propose a new general-purpose sensor processor architecture, which we call the Subliminal Processor. On the circuit side, subthreshold operation is known to exhibit an optimal energy point (Knin)- However, propagation delay also becomes more sensitive to process variation and can reduce the energy scaling gain. We conduct thorough analysis on how supply voltage and operating frequency impact energy efficiency in a statistical context. With careful library cell selection and robust static RAM design, the Subliminal Processor operates correctly down to 200 mV in a 0.13-mum technology, which is sufficiently low to operate at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> . Silicon measurements of the Subliminal Processor show a maximum energy efficiency of 2.6 pJ/instruction at 360 mV supply voltage and 833 kHz operating frequency. Finally, we examine the variation in frequency and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> across die to verify our analysis of adaptive tuning of the clock frequency and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> for optimal energy efficiency.

900 mV differential class AB OTA for switched opamp applications

A novel fully differential class AB OTA in standard CMOS for application with the switched opamp technique is presented. It makes use of a current buffer loop in the input stage as a low voltage current mirror. A new common mode feedback error amplifier, especially suited for the class AB OTA, is also presented. It is based on a differential stage of which the concept is introduced here. A totally new way of switching the amplifiers is introduced as well. Simulations demonstrate the operation of these novel circuits down to a 900 mV supply voltage.