Muthukrishnan-Stroud Gates Research Articles

Qutrit representation of quantum images: new quantum ternary circuit design

Quantum computation is growing in significance and proving to be a powerful tool in meeting the high real-time computational demands of classical digital image processing. However, extensive research has been done on quantum image processing, mainly rooted in binary quantum systems. In this paper, we propose a new quantum ternary image circuit based on the analysis of the existing qutrit representation of quantum images. The proposed design utilizes ternary shift gates and ternary Muthukrishnan–Stroud gates, with the belief that this circuit can be used for ternary quantum image processing. This study makes a significant improvement compared to the existing counterpart in terms of quantum cost, the number of constant inputs, and garbage outputs, which are all essential parameters in quantum circuit design.

Efficient design of quaternary quantum comparator with only a single ancillary input

Circuit design with no energy dissipation is possible in the reversible logic. Also, using the quantum multiple-valued logic in the design of circuits due to the reduction of circuit width leads to the smaller chip area and lower power consumption. Quaternary reversible logic potentially has several advantages in comparison to the equivalent ternary and binary quantum technologies. Hence, the quaternary quantum technology is a promising choice for the future digital system design. Here, the authors proposed an efficient design of 1-qudit and n -qudit quantum comparators. The comparator module is widely used in search conditions, such as Grover's quantum search algorithm in quantum computing. The proposed circuits were better than their existing counterparts in terms of quantum cost, the number of constant inputs, the number of garbage outputs, and hardware complexity. To design these circuits, they have used 1-qudit gates and 2-qudit Muthukrishnan-Stroud gates. The efficiency of their proposed circuits was reported.

Quantum Ternary Multiplication Gate (QTMG): Toward Quantum Ternary Multiplier and a New Realization for Ternary Toffoli Gate

The designs using ternary logic exploit its logarithmic reduction in the number of qudits compared with the binary circuits. In this paper, we propose quantum ternary multiplication gate. We term it as QTMG. Then we present the symbol and the realization of QTMG. Researchers will be able to use this gate as well as its symbol and realizations in their future studies. We also present a new realization of ternary Toffoli gate in specific state. Moreover, in this paper, we propose 1-qutrit multiplier circuit. The symbol and the realization of the proposed 1-qutrit multiplier circuit are also provided. Afterward, we proposed ternary partial products generation circuit (TPPG) and summation network circuit in order to design quantum ternary 2-qutrit multiplier circuit. Overall, the proposed design of QTMG in this paper is suggested for the first time. In addition, the proposed realization of ternary Toffoli gate, TPPG, summation network and 2-qutrit multiplier circuits are compared with the existing designs and the improvements are reported. The proposed gate and circuits are realized using macro-level ternary gates which are built on the top of the ion-trap realizable 1-qutrit gates and 2-qutrit Muthukrishnan–Stroud gates.

Quaternary Quantum/Reversible Half-Adder, Full-Adder, Parallel Adder and Parallel Adder/Subtractor Circuits

Multiple valued quantum logic is a promising research area in quantum computing technology having several advantages over binary quantum logic. Adder circuits as well as subtractor circuits are the major components of various computational units in computers and other complex computational systems. In this paper, we propose a quaternary quantum reversible half-adder circuit using quaternary 1-qudit gates, 2-qudit Feynman and Muthukrishnan-Stroud gates. Then we propose a quaternary quantum reversible full adder and a quaternary quantum parallel adder circuit. In addition, we propose a quaternary quantum reversible parallel adder/subtractor circuit. The proposed designs are compared with existing designs and improvements in terms of hardware complexity, quantum cost, number of constant inputs and garbage outputs are reported.

A Novel Design of a Multiplier Using Reversible Ternary Gates

ABSTRACT Reversible ternary circuit design is now being taken into consideration for its application within the quantum computer and other technologies associated with the nanotechnology domain, in addition to the advantages of the ternary logic application as opposed to binary logic. Multiplier circuit is one of the most important computing circuit in the ALU. Therefore, the circuit optimization for the multiplication will lead to efficient processor. In this paper, the reversible circuit for multiplication of two unsigned two-digit ternary numbers has been proposed. To construct reversible ternary multiplier, a new component termed TPPG with the quantum cost of 13 for partial product generation was proposed. In addition, we have introduced four new blocks of reversible ternary adder with the quantum cost of 11, 10, 7, 5 and one constant input, which can be used in the proposed multiplier circuit. We attempted to optimize the design of the circuits in terms of quantum cost, a number of primitive gates, constant inputs, and garbage outputs as far as possible. To realize all proposed circuits, one-qutrit shift gates and two-qutrit Muthukrishnan-Stroud gates were used.

A novel design of a ternary coded decimal adder/subtractor using reversible ternary gates

In recent years, an outstanding amount of interest has been given to reversible circuits. Their applications in distinctive fields that include digital circuit design with low-power consumption, computational circuit design in quantum computer and DNA-based computations are of high significance. Because of advantages of ternary circuits over binary circuits, such as reducing the complexity of interconnects, smaller chip area and reducing the number of quantum cells for the quantum circuit, ternary logic is suggested to construct new compact circuits. Also, in quantum technology, without any restrictions with the same physical phenomena that binary circuits are implemented, new circuits can be implemented in ternary logic. Circuit design for decimal calculations, which includes addition and subtraction of decimal numbers, has continually been the interest of digital circuit designers. In reversible ternary computation, the reversible circuits for decimal calculations have been less studied. In this paper, a reversible ternary adder/subtractor circuit for the addition/subtraction of decimal digits in radix three is proposed. Ternary Coded Decimal (TCD) codes are used to display decimal inputs and outputs. In circuit implementation, first by removing the unused inputs and outputs in the required ternary adders in the TCD Adder, three blocks of reversible 3-qutrit ternary adder with the quantum cost of 29, 22, 14 and constant inputs of 0, 1, and 0 were presented, then an optimal circuit for the TCD detector with a quantum cost of 16 was introduced. The proposed TCD detector has 23% improvement in quantum cost as compared to the existing design. By applying these in the design of the reversible TCD Adder, a more optimal reversible TCD Adder circuit than the existing design was presented resulting in a 31% improvement in quantum cost and 58% improvement in the number of constant inputs. Finally, decimal 9's complement circuit for the subtraction of two decimal numbers was proposed. In the proposed TCD Adder/Subtractor, the new proposed TCD Adder and decimal 9's complement circuits were used. To realize all proposed circuits, 1-qutrit shift gates and 2-qutrit Muthukrishnan-Stroud gates, which are realized in ion-trap technology in quantum computers, were used.

Designing new ternary reversible subtractor circuits

The reducing of the width of quantum reversible circuits makes multiple-valued reversible logic a very promising research area. Ternary logic is one of the most popular types of multiple-valued reversible logic, along with the Subtractor, which is among the major components of the ALU of a classical computer and complex hardware. In this paper the authors will be presenting an improved design of a ternary reversible half subtractor circuit. The authors shall compare the improved design with the existing designs and shall highlight the improvements made after which the authors will propose a new ternary reversible full subtractor circuit. Ternary Shift gates and ternary Muthukrishnan–Stroud gates were used to build such newly designed complex circuits and it is believed that the proposed designs can be used in ternary quantum computers. The minimization of the number of constant inputs and garbage outputs, hardware complexity, quantum cost and delay time is an important issue in reversible logic design. In this study a significant improvement as compared to the existing designs has been achieved in as such that with the reduction in the number of ternary shift and Muthukrishnan-Stroud gates used the authors have produced ternary subtractor circuits.

Novel Quaternary Quantum Decoder, Multiplexer and Demultiplexer Circuits

Multiple valued logic is a promising approach to reduce the width of the reversible or quantum circuits, moreover, quaternary logic is considered as being a good choice for future quantum computing technology hence it is very suitable for the encoded realization of binary logic functions through its grouping of 2-bits together into quaternary values. The Quaternary decoder, multiplexer, and demultiplexer are essential units of quaternary digital systems. In this paper, we have initially designed a quantum realization of the quaternary decoder circuit using quaternary 1-qudit gates and quaternary Muthukrishnan-Stroud gates. Then we have presented quantum realization of quaternary multiplexer and demultiplexer circuits using the constructed quaternary decoder circuit and quaternary controlled Feynman gates. The suggested circuits in this paper have a lower quantum cost and hardware complexity than the existing designs that are currently used in quaternary digital systems. All the scales applied in this paper are based on Nanometric area.

Design of a Ternary Reversible/Quantum Adder using Genetic Algorithm

Typical methods of quantum/reversible synthesis are based on using the binary character of quantum computing. However, multi-valued logic is a promising choice for future computer technologies, given a set of advantages when comparing to binary circuits. In this work, we have developed a genetic algorithm-based synthesis of ternary reversible circuits using Muthukrishnan-Stroud gates. The method for chromosomes coding that we present, as well as a judicious choice of algorithm parameters, allowed obtaining circuits for half-adder and full adder which are better than other published methods in terms of cost, delay times and amount of input ancillary bits. A structure of the circuits is analyzed in details, based on their decomposition.

Synthesis of quaternary reversible/quantum comparators

Multiple-valued quantum circuits are promising choices for future quantum computing technology, since they have several advantages over binary quantum circuits. Quaternary logic has the advantage that classical binary functions can be very easily represented as quaternary functions by grouping two bits together into quaternary values. Grover's quantum search algorithm requires a sub-circuit called oracle, which takes a set of inputs and gives an output stating whether a given search condition is satisfied or not. Equality, less-than, and greater-than comparisons are widely used as search conditions. In this paper, we show synthesis of quaternary equality, less-than, and greater-than comparators on the top of ion-trap realizable 1-qudit gates and 2-qudit Muthukrishnan-Stroud gates.

Quantum ternary parallel adder/subtractor with partially-look-ahead carry

Multiple-valued quantum circuits are a promising choice for future quantum computing technology since they have several advantages over binary quantum circuits. Binary parallel adder/subtractor is central to the ALU of a classical computer and its quantum counterpart is used in oracles - the most important part that is designed for quantum algorithms. Many NP-hard problems can be solved more efficiently in quantum using Grover algorithm and its modifications when an appropriate oracle is constructed. There is therefore a need to design standard logic blocks to be used in oracles - this is similar to designing standard building blocks for classical computers. In this paper, we propose quantum realization of a ternary full-adder using macro-level ternary Feynman and Toffoli gates built on the top of ion-trap realizable ternary 1-qutrit and Muthukrishnan-Stroud gates. Our realization has several advantages over the previously reported realization. Based on this realization of ternary full-adder we propose realization of a ternary parallel adder with partially-look-ahead carry. We also show the method of using the same circuit as a ternary parallel adder/subtractor.