Multi-wafer Reactor Research Articles

SmartSiC™ Substrates: A Boon to Drain Metallization Process

We present results of epitaxial characterization and benchmarking of Silicon Carbide (SiC) epitaxial layers grown on both 6-inch commercially available SiC substrate and on SOITEC’s new generation SmartSiCTM substrate. Multi wafer reactor was utilized to avoid run-to-run variation. Schottky Barrier Diodes (SBD) and electrical test vehicles were fabricated to extract ideality factor, barrier height and ohmic contact resistance for benchmarking.

Manufacturing of Gallium Nitride Thin Films in a Multi-Wafer MOCVD Reactor

Abstract Gallium nitride (GaN) thin films have attracted considerable attention for manufacturing optical and electronic devices. They have wide bandgap and superb performance in these applications. The reliability and durability of optoelectronic devices depend on the quality of the GaN thin films. The metal-organic chemical vapor deposition (MOCVD) process is a common manufacturing technique for fabricating high-quality thin films. By manipulating the operating conditions and the reactor design, one can control the deposition rate and the uniformity of the thin film. In this paper, the manufacturing process for GaN thin films in a multi-wafer MOCVD reactor is simulated based on the three-dimensional computational model of an experimental system which provides data for validation as well as realistic design parameters. The reactor pressure and the flow rate of the precursor, trimethyl-gallium (TMG), significantly affect the deposition rate and film uniformity. The incursion of impurities in the deposition can be reduced by increasing the volumetric ratio of NH3 to TMG (V/III) and reducing the reactor pressure. The deposition rate and quality of the thin film are enhanced using an appropriate mixture of H2 and N2 as the carrier gas. The design of the inlet can also be varied to improve the utilization of metal-organic precursors and increase the deposition rate. This paper presents and discusses results on these aspects for this important manufacturing process. Thus, it leads to a better understanding of the basic mechanisms involved and provides guidelines for obtaining high deposition rates with high film quality in practical chemical vapor deposition reactors.

Direct-simulation Monte Carlo modeling of reactor-scale gas-dynamic phenomena in a multiwafer atomic-layer deposition batch reactor

Atomic layer deposition (ALD) using multiwafer batch reactors has now emerged as the manufacturing process of choice for modern microelectronics at a massive scale. Stringent process requirements of thin film deposition uniformity within wafer (WiW) and wafer–wafer (WTW) in the batch, film conformity along submicrometer wafer features, thin film quality, and the utilization of expensive precursors in the reactor dictate ALD reactor design and process parameter optimization. This paper discusses a particle-based direct-simulation Monte Carlo (DSMC) of the full reactor scale simulation that overcomes the low Knudsen number limitation of typical continuum computational fluid dynamics approaches used for modeling low-pressure ALD reactors. A representative industrial multiwafer batch reactor used for the deposition of Si-based thin films with N2 and Si2Cl6 (hexachlorodisilane) as process feed gases with pressures in the range 43–130 Pa and a uniform reactor temperature of 600 °C is simulated. The model provides detailed insights into the flow physics associated with the transport of the precursor species from the inlets, through wafer feed nozzles, into the interwafer regions, and finally through the outlet. The reactor operating conditions are shown to be in the slip/transitional flow regime for much of the reactor volume and especially the feed gas nozzle and interwafer regions (where the Knudsen number approaches ∼0.2), justifying the need for a high-Knudsen number DSMC approach as in this work. For the simulated conditions, the nonuniformity of precursor species immediately above the wafer surface is predicted to be within <1% for a given wafer and <2% across the entire multiwafer stack. Results indicate that higher pressure degrades WiW and WTW uniformity. A reactor flow efficiency is defined and found to be ∼99%, irrespective of the chamber pressure.

Planar mid-infrared InAsSb photodetector grown on GaAs substrates by MOCVD

Planar mid-wavelength infrared photodetectors with InAsSb absorber grown on GaAs substrates are demonstrated. Epilayer growth and diffusion of zinc in InAsSb were carried out in a multi-wafer MOCVD reactor. In addition to the planar p+n junction defined by Zn diffusion, a Schottky junction was integrated to reduce the dark current and improve the optical responsivity. At 85 K, a cutoff wavelength greater than 5 μm was achieved and specific detectivity D* was estimated to be 5.0 × 1011 cm·Hz1/2 W−1 at 4.1 μm under zero bias condition. Furthermore, the photodetector can operate up to 160 K with a D* of 1.0 × 109 cm·Hz1/2 W−1.

Early history of MOVPE reactor development

MOVPE technology has rapidly grown from a laboratory research novelty in the 1960’s to the dominant production method for epitaxial materials used in high-performance compound semiconductors devices. In order for MOVPE to be adopted as an efficient and high-yield process, the MOVPE reactor had to be designed and operated in a manner to produce uniform epitaxial layer structures with a high degree of controllability and reproducibility. In commemoration of 50 years of MOVPE technological advancement, this paper reviews the early history of MOVPE reactor development and foundational advances that were critical for development of multi-wafer capacity production reactors having high yield and reproducibility.

Control over the optical and electronic performance of GaAs/AlGaAs QWIPs grown by production MBE

Commercial production of quantum well infrared detectors (QWIPs) requires targeting specific detector dark current densities and cutoff wavelengths. Molecular beam epitaxy (MBE) allows a tight control over the quantum-well structure. This manuscript discusses the growth of the long-wave infrared (LWIR) QWIP detectors on the multi-wafer MBE reactors at IntelliEpi. We address the tuning of the cutoff wavelength by adjusting of the thickness of the GaAs quantum well (QW) layer and the composition of the AlGaAs barrier. The control over the dark current densities is examined through the correlation with the doping levels and the detector cutoff wavelength.

(Invited) Progress in Buried Grid Technology for Improvements in on-Resistance of High Voltage SiC Devices

Silicon Carbide (SiC) is regarded as the material of choice for high voltage (>1kV) power devices due to its material properties, mature fabrication technology, and availability of 150mm diameter wafer material. SiC power devices like Schottky barrier diodes (SBDs) and MOSFETs with voltage ratings of 1700V and current handling capabilities of 50A and more are commercially available from several vendors. Commercial SiC SBDs are based on the merged p-n junction and Schottky (MPS) concept or the junction barrier controlled Schottky (JBS) concept. Commercial MOSFETs utilize the VDMOS concept having a vertical device design with lateral channel and the UMOS concept with vertical channel at trench sidewalls. Common for these device concepts is that the electric field at device areas like Schottky contacts and MOS interfaces is relatively high and limits often the device performance. This leads to that the full potential of SiC devices cannot be realized. For example, in planar surface p-grid JBS diode structures the protection of the Schottky areas from high electric field is not sufficient and result in high leakage currents limiting the SOA in terms of junction and operation temperature. In addition, the edge termination is realized at the top surface of the SiC material and has to be carefully designed to not exceed the limitations of passivation and packaging materials. Buried grid technology is suggested to decrease the electric field at field sensitive device areas and to move areas of high electric field into the SiC bulk. It was demonstrated for SiC JBS diodes that buried grid technology gives more than three orders of magnitude lower leakage currents even at high temperature operation due to the superior shielding effect. The drawback is that the introduction of the buried grid increases the total resistance and therefore increases the forward voltage drop at rated current and the conduction losses. In this paper, we review our work on improving the on-state characteristics of buried grid SiC devices. The work is mainly done for buried grid JBS-diodes (BG-JBS), but can be applied also to buried grid MOSFETs (BG-MOSFET). For the BG-SiC devices, a p-grid is fabricated either by aluminum implantation followed by high temperature anneal or trench etching with subsequent epitaxial re-growth and planarization to fill up etched trenches with p-type material. As a final step, the p-grid is buried by another re-growth step of a thin n-layer. The epitaxial grid approach is done with Ascatron’s 3D-SiC core technology based on embedded epitaxial growth techniques, replacing high dose ion implantation at elevated temperatures and high temperature anneal by epitaxial growth in trenches. For cost-effective fabrication, this process should be performed in multi-wafer reactors. For devices with blocking capability of up to 1700V, we typically employ floating ring type edge termination formed simultaneously with the active area p-grid. For higher voltages than 1700V we suggest to use a JTE type edge termination formed by ion implantation in the same layer as the p-grid. Hence, the edge termination is also buried in the SiC bulk. By carefully designing the drift and re-growth layers as well as the epitaxial or implanted p-grid, the fabrication process can be optimized in terms of trade-off between current handling capability in forward and blocking behavior and leakage current in reverse. In addition, the size and spacing of the p-areas are critical parameters to optimize the BG-SiC device performance to realize maximum current handling capability at forward voltage similar or below surface grid devices and minimum leakage current especially for high temperature operation. To reduce the forward voltage, we employed relatively high n-doping in the channel regions between the p-islands and optimized the drift and re-grown top layer doping. Due to the superior material quality, epitaxial grown BG-structures result in increased bipolar injection at high current densities and thus give improved surge current capabilities. In addition, epitaxial p-n junctions show lower leakage currents than implanted ones.

Reduction of epitaxial defects on 4°-off 4H[sbnd]SiC homo-epitaxial growth by optimizing in-situ etching process

The investigations of in-situ etching of 4HSiC epi-growth on 4° off-axis 100 mm diameter substrates under different conditions have been carried out in a commercial warm-wall multi-wafer planetary reactor. The surface morphologies of the as-etched substrates have been characterized by atomic force microscopy on 20 × 20 μm2. Based on the step height and roughness mean square, the best etching condition for 4HSiC 4° off-axis substrates was determined to be H2 + HCl at 1500 °C for 10 min. With the optimized in-situ etching process, high quality 4HSiC epitaxial layers with excellent surface morphology have been obtained, and the defect density is lowered to 0.45 cm−2 resulting in a projected 2 × 2 mm die yield of ∼98%.

150 mm 4H-SiC Epitaxial Layer Growth in a Warm-Wall Planetary Reactor

Homo-epitaxial growth of 4H-SiC on 4o off-axis 150 mm diameter substrates has been performed in a commercial warm-wall multi-wafer planetary reactor. Based on our well developed 100 mm 4H-SiC epitaxial growth process, which can achieve excellent thickness and doping uniformities (δ/mean) of <1% and <5%, respectively, the growth process and hardware were further fine-tuned and improved for 150 mm 4H-SiC homoepitaxy. After the improvement, the 6 to7 μm thick epilayer uniformity has reached 1.1% with a 5mm edge exclusion while the doping uniformity has improved to 16.5% (<10%) with an edge exclusion of 5 mm (10mm), respectively. Surface roughness of the as-grown 150 mm 4H-SiC epitaxial layer has an RMS value of 0.12 nm scanned by AFM on 20×20 μm2 areas. Homo-epitaxial growth on C-face 150 mm 4H-SiC substrates has also been carried out. Other than the doping concentration and uniformity, the other results are very close to the epi-growth on Si-face.

50 μm-Thick 100 mm 4H-SiC Epitaxial Layer Growth by Warm-Wall Planetary Reactor

Homo-epitaxial growth of 50 μm-thick 4H-SiC on 4° off-axis 100 mm substrates have been demostrated by using a commercial warm-wall multi-wafer planetary reactor (Aixtron 2800 G4). With optimized process, epitaxial layer with an average thickness of 48.146 μm and doping level of 8.39×1014/cm3 are obtained. The thickness uniformity with an edge exclusion of 5 mm are 1.30% (σ/mean) and 2.17% (max-min/max+min), and the doping level uniformity are 4.66% (σ/mean) and 6.95% (max-min/max+min), respectively. Surface roughness of the as-grown 50 μm-thick epitaxial layer has an RMS value of 0.606 nm with one step bunching on the 20×20 μm2 areas. This initial effort on thick 4H-SiC homoepitaxial growth indicates that this comercial multi-wafer planetary reactor has the potential for mass production of SiC epiwafers for 5000 V and above power devices.

Progress in Large-Area 4H-SiC Epitaxial Layer Growth in a Warm-Wall Planetary Reactor

Results are presented for epitaxial SiC layers grown on 100 mm and 150 mm wafers suitable for power devices by CVD using a VP2800WW multi-wafer reactor with 10×100mm and 6×150mm configurations. We have demonstrated continuous improvement in uniformity for thickness and doping, as well as in defect reduction in standard epitaxy on 100 mm wafers. Thickness and doping sigma/mean values of <1.5% and <8%, respectively, could be routinely achieved. Doping and thickness measurements of 30 μm layer growth show results similar to standard epilayer growth. The averaged projected site yields of 80% for 5x5 mm2 and of 96% for 2x2 mm2 correspond to a low epitaxial defect density of <1 cm="" sup="">-2 in 30μm thick epilayers. Epilayer structures for bipolar devices like PiN diodes and BJTs are shown. The interface regions between nitrogen doped and aluminum doped layers show an abrupt transition of dopant concentration. Wafer quality of 100 mm and 150 mm material is presented as an important base factor for excellent epitaxial layer quality. It is shown that 150 mm substrates exhibit TSD and BPD densities very similar to the 100 mm materials. Site counts for TSDs and BPDs on sample wafers show dislocations densities of 500 cm-2 and 300 cm-2, respectively. After CVD process optimization, a thickness uniformity (sigma/mean) of <1.5% and a doping uniformity of <13% was achieved on epitaxial layers on 150mm.

Design of a Multi-Wafer Reactor for Supercritical Fluid Deposition of Cu in Mass Production: (1) Reaction Mechanism and Kinetics

Design of a Multi-Wafer Reactor for Supercritical Fluid Deposition of Cu in Mass Production: (1) Reaction Mechanism and Kinetics

Design of a Multi-Wafer Reactor for Supercritical Fluid Deposition of Cu in Mass Production: (2) Benchmarks for Single- and Multiple-Wafer Reactors

Design of a Multi-Wafer Reactor for Supercritical Fluid Deposition of Cu in Mass Production: (2) Benchmarks for Single- and Multiple-Wafer Reactors

High Uniformity with Reduced Surface Roughness of Chloride Based CVD Process on 100mm 4° Off-Axis 4H-SiC

In this work we present the epitaxial growth of 4H-SiC on 100mm 4° off-axis substrates grown in a multi-wafer CVD planetary reactor. Highly uniform epitaxial layers having thickness and doping uniformities of 1.7% and 1.4% respectively were grown in the production reactor with optimized process conditions at 8µm/hr and 30µm/hr growth rates. Process optimizations resulted in epitaxial layers with surface roughness (RMS) of 0.32nm. Epitaxial layers with a thickness of 53µm grown with a 30µm/hr growth process had minimal degradation in surface roughness (RMS of 0.39nm).

Silicon Epitaxial Growth Rate and Transport Phenomena in a Vertical Stacked-Type Multi-Wafer Reactor

The silicon epitaxial growth rate in a trichlorosilane–hydrogen system using a vertical stacked-type multi-wafer reactor, having more than 100 substrate pieces, together with two horizontal gas inlet nozzles for each substrate, was studied by means of numerical calculations. In this study, the authors developed a compact model that consisted of the minimal set of reactor parts, by taking into account the gas flow condition around the stacked susceptors. Because the direction of the gases horizontally injected to the substrate is bent by the gas flowing downward along the stacked susceptors, a part of the horizontally injected gas in the downstream positions is forced to directly go to the exhaust, and not to the substrate. The wafer-to-wafer uniformity of epitaxial thickness is expected to be improved by means of finely adjusting the susceptor position, particularly at the downstream positions.

Multiwafer zinc diffusion in an OMVPE reactor

We study diffusion of zinc into InP in a multiwafer OMVPE reactor using dimethylzinc as the diffusant source. The resulting diffusion profiles are measured by electrochemical capacitance–voltage profiling and by secondary ion mass spectrometry and compared with cleaved cross-sections imaged by scanning electron microscopy. Very good uniformity of the diffusion profile is achieved, with variation across a 3in. wafer as little as 5%. The dependence of the diffusion depth and Zn concentration on the diffusion temperature, partial pressure of dimethylzinc, and diffusion time are reported. We observe an enhancement of the diffusion depth in area-selective diffusion of planar devices, compared to the depth obtained for blanket diffusion.

Liquid Injection MOCVD Grown Binary Oxides and Ternary Rare-Earth Oxide as Alternate Gate-Oxides for Logic Devices

ZrO2, HfO2 and DyScO3 thin films having thickness in the range 2-20 nm were grown on SiOx/Si(100) substrates in a multi-wafer planetary MOCVD reactor combined with a liquid delivery system using engineered precursors. Growth rate, surface morphology, crystal structure, crystal density of the as-deposited films were analysed as a function of deposition temperature. The influence of post deposition annealing on the densification and crystallization was studied. Electrical properties of MIS capacitor structures are also discussed. Results on the optimised gate stack of Pt/ZrO2/SiOx/Si, Pt/HfO2/SiOx/Si, Pt/DyScO3/SiOx/Si are finally compared; and DyScO3 seems to be promising high-k material candidate compared to Group-IVB oxides for the coming technology nodes.

Scaling of Chlorosilane SiC CVD to Multi-Wafer Epitaxy System

A SiC epitaxy process based on chlorosilane/propane chemistry has been successfully transferred from a single-wafer R&D system to a multi-wafer CVD reactor. The optimized process results in very smooth epi surface (RMS~0.24nm) and minimum surface pits (less than 0.5/cm2). Both n-type and p-type doping in a wide range are demonstrated using nitrogen and aluminum, respectively. The high performance benchmarks for thickness uniformity (intra-wafer variation <1% and inter-wafer variation <1%) and doping uniformity (intra-wafer variation <6% and inter-wafer variation <3%) are achieved on 5 x 3-inch wafers. The carrier lifetime in these epilayers measured by μ-PCD is over 5 μs, the longest value reported so far for SiC epitaxial wafers.

Transient ALD simulations for a multi-wafer reactor with trenched wafers

For a large multi-wafer vertical batch ALD reactor, transient, 3-dimensional, multi-scale simulations have been performed for the TEMAH pulse step during a HfO 2 ALD process. A bi-directional, multi-scale coupling has been established between continuum reactor scale simulations and molecular trench scale simulations. For describing the molecular deposition process inside narrow deep trenches, two different models have been developed and implemented as boundary condition for the flow simulation: an analytical model based on the model proposed by Gordon, and a numerical Knudsen diffusion model. Both trench models have been validated against DSMC simulation results for a single trench. Based on the 3D reactor simulation results, important timescales in the complete process are identified. It is found that several timescales are of the same order of magnitude, rendering predictions based on engineering rules more difficult. Timescales for trenched wafers are found to be much larger than for flat wafers, leading to much longer required cycle times.

Modelling of group-III nitride MOVPE in the closed coupled showerhead reactor and Planetary Reactor ®

The modelling and subsequent experimental validation of nitride growth processes in commercial, production scale multi-wafer reactors is investigated with focus on group-III nitride compounds GaN and InGaN. The paper also deals with the development of group-III nitride growth processes at elevated process pressures, highlighting the effects of gas-phase nucleation phenomena on the growth efficiency of GaN. In addition, the latest hardware and process improvements to the Planetary Reactor ® technology are presented, with focus on the development using a modelling approach, of a new gas injector design for III-nitride growth. Subsequent experimental validation of the new injector design, and its flexibility to changing process regimes for GaN and InGaN will be demonstrated for the 42×2″ Planetary Reactor ®.