Multiple-valued Logic Research Articles

The Synopsis of Soft Computing.

The traditional method of problem-solving, known as hard computing, is limited in its ability to handle modern digital technology and real-world problems accurately. Soft computing, a newer paradigm, offers a more versatile approach by utilizing multi-valued logic and human knowledge to solve complex, nonlinear problems efficiently. Unlike hard computing, soft computing can handle imprecise data and uncertainty effectively. This methodology has been successfully applied across various sectors, including scientific, industrial, and medical fields, providing more accurate results. Soft computing is good for its contributions to revolutionizing problem-solving techniques, being tolerant of imprecision, uncertainty, and linguistic variables, and offering approximate solutions to intricate problems.

On implicit extensions in many-valued logic

On implicit extensions in many-valued logic

Research on Multiplication Routine Based on Reconfigurable Four-Valued Logic Processor

Despite the indispensable role of traditional electronic computers in modern society, their limitations in parallel processing capabilities, bit-width constraints, and processor bit-width are becoming increasingly apparent, especially when handling large-scale datasets and complex computational tasks. Although hardware technology and algorithm optimization continue to advance, the arithmetic units of traditional computers—adders—remain constrained by carry delay and bit-width limitations. This bottleneck is particularly pronounced in multiplication operations, mainly when adders are used for partial product accumulation. However, since 2018, the emergence of a new type of Reconfigurable Four-Valued Logic Electronic Processor (RFLEP) has provided a potential solution to these traditional limitations. With its large processor bit-width, flexible bit grouping capabilities, and dynamic hardware function reconfiguration features, this processor has brought revolutionary changes to the field of computing. In this context, this paper proposes and implements a Reconfigurable Four-Valued Logic Multiplication Routine (RFLMR) tailored explicitly for the RFLEP. The RFLMR utilizes the Modified Signed-Digit (MSD) representation method in multi-valued logic combined with the M transformation in four-valued logic to generate partial products. These partial products are then efficiently summed in parallel using the JW-MSD parallel adder, achieving the rapid execution of multiplication operations. Experimental results demonstrate that the multiplication routine based on the RFLEP performs multiplication operations accurately and meets theoretical expectations regarding implementation efficiency and performance. This research not only provides new ideas for developing next-generation high-performance computing systems but also paves the way for exploring more efficient and powerful computing models, heralding a profound transformation in future computing technology.

Inferential Interpretations of Many-Valued Logics

Inferential Interpretations of Many-Valued Logics

Reconfigurable Vertical Phototransistor with MoTe2 Homojunction for High-Speed Rectifier and Multivalued Logical Circuits.

The most reported two-dimensional (2D) reconfigurable multivalued logic (RMVL) devices primarily involve a planar configuration and carrier transport, which limits the high-density circuit integration and high-speed logic operation. In this work, the vertical transistors with reconfigurable MoTe2 homojunction are developed for low-power, high-speed, multivalued logic circuits. Through top/bottom dual-gate modulation, the transistors can be configured into four modes: P-i-N, N-i-P, P-i-P, and N-i-N. The reconfigurable rectifying and photovoltaic behaviors are observed in P-i-N and N-i-P configurations, exhibiting ideal diode characteristics with a current rectification ratio over 105 and sign-reversible photovoltaic response with a photoswitching ratio up to 7.44 × 105. Taking advantage of the seamless homogeneous integration and short vertical channel architecture, the transistor can operate as an electrical switch with an ultrafast speed of 680 ns, surpassing the conventional p-n diode. The MoTe2 half-wave rectifier is then applied in high-frequency integrated circuits using both square wave and sinusoidal waveforms. By applying an electrical pulse with a 1/4 phase difference between two input signals, the RMVL circuit has been achieved. This work proposes a universal and reconfigurable vertical transistor, enabled by dual-gate electrostatic doping on top/bottom sides of MoTe2 homojunction, suggesting a high integration device scheme for high-speed RMVL circuits and systems.

A hot-emitter transistor based on stimulated emission of heated carriers

Hot-carrier transistors are a class of devices that leverage the excess kinetic energy of carriers. Unlike regular transistors, which rely on steady-state carrier transport, hot-carrier transistors modulate carriers to high-energy states, resulting in enhanced device speed and functionality. These characteristics are essential for applications that demand rapid switching and high-frequency operations, such as advanced telecommunications and cutting-edge computing technologies1–5. However, the traditional mechanisms of hot-carrier generation are either carrier injection6–11 or acceleration12,13, which limit device performance in terms of power consumption and negative differential resistance14–17. Mixed-dimensional devices, which combine bulk and low-dimensional materials, can offer different mechanisms for hot-carrier generation by leveraging the diverse potential barriers formed by energy-band combinations18–21. Here we report a hot-emitter transistor based on double mixed-dimensional graphene/germanium Schottky junctions that uses stimulated emission of heated carriers to achieve a subthreshold swing lower than 1 millivolt per decade beyond the Boltzmann limit and a negative differential resistance with a peak-to-valley current ratio greater than 100 at room temperature. Multi-valued logic with a high inverter gain and reconfigurable logic states are further demonstrated. This work reports a multifunctional hot-emitter transistor with significant potential for low-power and negative-differential-resistance applications, marking a promising advancement for the post-Moore era.

Belief Horn merging operators: Characterization results and implementations

The paper contributes to the study of belief merging in many-valued logics, taking both a theoretical and implementation approach motivated by applications in real-world scenarios. We focus, in particular, on the Horn fragment of signed logic. On the one hand, a characterization of the class of models of a signed regular Horn formula and a sufficient condition for a signed Horn merging operator to satisfy logical IC-postulates are provided. On the other hand, an implementation of the belief merging process in the signed regular Horn fragment is presented.

Two-Dimensional SnSe2(1-x)S2x/MoTe2 Antiambipolar Transistors with Composition Modulation for Multivalued Inverters.

Two-dimensional (2D) van der Waals heterostructures that embody the electronic characteristics of each constituent material have found extensive applications. Alloy engineering further enables the modulation of the electronic properties in these structures. Consequently, we envisage the construction and modulation of composition-dependent antiambipolar transistors (AATs) using van der Waals heterostructures and alloy engineering to advance multivalued inverters. In this work, we calculate the electron structures of SnSe2(1-x)S2x alloys and determine the energy band alignment between SnSe2(1-x)S2x and 2H-MoTe2. We present a series of vertical AATs based on the SnSe2(1-x)S2x/MoTe2 type-III van der Waals heterostructure. These transistors exhibit composition-dependent antiambipolar characteristics through the van der Waals heterostructure, except for the SnSe2/MoTe2 transistor. The peak current (Ipeak) decreases from 43 nA (x = 0.25) to 0.8 nA (x = 1) at Vds = -2 V, while the peak-to-valley current ratio (PVR) increases from 4.5 (x = 0.25) to 6.7 × 103 (x = 1) with a work window ranging from 30 to 47 V. Ultimately, we successfully apply several specific SnSe2(1-x)S2x/MoTe2 devices in binary and ternary logic inverters. Our results underscore the efficacy of alloy engineering in modulating the characteristics of AATs, offering a promising strategy for the development of multivalued logic devices.

Enhanced CPU Design for SDN Controller.

Software-Defined Networking (SDN) revolutionizes network management by decoupling control plane functionality from data plane devices, enabling the centralized control and programmability of network behavior. This paper uses the ternary system to improve the Central Processing Unit (CPU) inside the SDN controller to enhance network management. The Multiple-Valued Logic (MVL) circuit shows remarkable improvement compared to the binary circuit regarding the chip area, propagation delay, and energy consumption. Moreover, the Carbon Nanotube Field-Effect Transistor (CNTFET) shows improvement compared to other transistor technologies regarding energy efficiency and circuit speed. To the best of our knowledge, this is the first time that a ternary design has been applied inside the CPU of an SDN controller. Earlier studies focused on Ternary Content-Addressable Memory (TCAM) in SDN. This paper proposes a new 1-trit Ternary Full Adder (TFA) to decrease the propagation delay and the Power-Delay Product (PDP). The proposed design is compared to the latest 17 designs, including 15 designs that are 1-trit TFA CNTFET-based, 2-bit binary FA FinFET-based, and 2-bit binary FA CMOS-based, using the HSPICE simulator, to optimize the CPU utilization in SDN environments, thereby enhancing programmability. The results show the success of the proposed design in reducing the propagation delays by over 99% compared to the 2-bit binary FA CMOS-based design, over 78% compared to the 2-bit binary FA FinFET-based design, over 91% compared to the worst-case TFA, and over 49% compared to the best-case TFAs.

Configurable anti-ambipolar photoresponses for optoelectronic multi-valued logic gates

Anti-ambipolar transistors (AATs) are the leading platform for the paradigm shift from binary to multi-valued logic (MVL) circuits, increasing circuit integration density and data processing capacity. However, most AATs with p–n heterojunctions present limited controllability of the transconductance peak, which is key to MVL operation. Here, we report optically configurable AAT/bi-AAT photoresponses implemented with an InSe field-effect transistor for potential MVL operations. The charge trapping and detrapping processes incorporated with manually introduced trap states form the AAT peaks. Furthermore, leveraging a symmetric device configuration, the dark current is significantly suppressed, and AAT photoresponses are highlighted. Contributed by two pathways of trap states, the AAT/bi-AAT photoresponses are switchable by incident optical wavelength. This dependence facilitates optical wavelength to be one of the logic inputs for MVL, based on which we propose circuit-free ternary logic gates in a single device that can achieve more than ∼6 and ∼19 times improved data density (1 bit per transistor) for NMAX and XNOR, compared with such circuits in a traditional binary design. This work realizes optically controlled AAT photoresponses, paving the way to exploit optical wavelength as a new degree of freedom in MVL computing, offering a route toward ultra-high-density, ultra-low-power, and optically programmable optoelectronic integrated circuits.

Problems Of Many-Valued Logic from The Point of View of The Theory of Socio-Cultural Code

It is shown that there are prerequisites for returning to the original interpretation of logic as the science of the laws of thought. Using the methods of the neural network theory of the noosphere, it is proved that the nature of thinking is significantly influenced by the socio-cultural code of the ethnic/social system. A connection is revealed between philosophical categories as basic undefined concepts and archetypes, understood according to Jung. It is proved that the formalization of the laws of thinking, built on multi-valued logic, should operate not only and not so much with the concepts of natural language, but with “reflection quanta” lying on the archetypal level of consciousness. It is shown that the category of truth underlying classical logic can also be interpreted as a “reflection quantum”, but which has undergone a formalization procedure. It is demonstrated how exactly the apparatus of multi-valued logic can be applied to identifying links between the "quanta of reflection", which can be considered as a generalization of the rules of reasoning established in classical logic, dating back to Aristotle. The category “Qi”, which underlies ancient Chinese philosophy and is inseparable from the Chinese sociocultural code, was used as an example. Meaning of this category in the version that is assimilated by European and Eurasian sociocultural codes is revealed.

Energy-efficient design of quaternary logic gates and arithmetic circuits using hybrid CNTFET-RRAM technology

Multi-valued logic (MVL) extends binary logic by providing a framework to represent complex systems with more than two truth values. MVL was introduced to confront the enormous interconnect issue associated with the binary logic in implementing the presnt day complex nanoelectronic architectures. This paper delves into the circuit design, computational aspects, and practical applications of the quaternary logic system, which is a type of MVL with four truth values. The multi-threshold property of carbon nanotube field-effect-transistors (CNTFETs), combined with the ability of resistive random-access memory (RRAM) to store multiple resistance values, has enabled the design of quaternary logic gates and arithmetic circuits. A new CNTFET-based design architecture has been proposed to implement the quaternary logic compatible with the existing technologies. Quaternary logic gates such as inverter, NAND, and NOR, and quaternary arithmetic circuits including decoder, half adder, and multiplier have been designed. The power-delay-product (PDP) of the proposed quaternary inverter, NAND, NOR, half adder, and multiplier is 62.38%, 93.4%, 80.29%, 14.79%, and 20% less than the least PDP of the quaternary designs under consideration. The static power reduction due to the effecciency of the design architecture and high OFF state resistance offered by integrating RRAM into the logic design was explored.The proposed circuits have been subject to various types of parameter variations to validate thir proper functionality in presence of these variations.

Many-valued coalgebraic logic over semi-primal varieties

We study many-valued coalgebraic logics with semi-primal algebras of truth-degrees. We provide a systematic way to lift endofunctors defined on the variety of Boolean algebras to endofunctors on the variety generated by a semi-primal algebra. We show that this can be extended to a technique to lift classical coalgebraic logics to many-valued ones, and that (one-step) completeness and expressivity are preserved under this lifting. For specific classes of endofunctors, we also describe how to obtain an axiomatization of the lifted many-valued logic directly from an axiomatization of the original classical one. In particular, we apply all of these techniques to classical modal logic.

Probabilistic Semantics and Calculi for Multi-valued and Paraconsistent Logics

Probabilistic Semantics and Calculi for Multi-valued and Paraconsistent Logics

Free Constructions in Hoops via $$\ell $$-Groups

AbstractLattice-ordered abelian groups, or abelian$$\ell $$ ℓ -groups in what follows, are categorically equivalent to two classes of 0-bounded hoops that are relevant in the realm of the equivalent algebraic semantics of many-valued logics: liftings of cancellative hoops and perfect MV-algebras. The former generate the variety of product algebras, and the latter the subvariety of MV-algebras generated by perfect MV-algebras, that we shall call $$\textsf{DLMV}$$ DLMV . In this work we focus on these two varieties and their relation to the structures obtained by forgetting the falsum constant 0, i.e., product hoops and DLW-hoops. As main results, we first show a characterization of the free algebras in these two varieties as particular weak Boolean products; then, we show a construction that freely generates a product algebra from a product hoop and a DLMV-algebra from a DLW-hoop. In other words, we exhibit the free functor from the two algebraic categories of hoops to the corresponding categories of 0-bounded algebras. Finally, we use the results obtained to study projective algebras and unification problems in the two varieties (and the corresponding logics); both varieties are shown to have (strong) unitary unification type, and as a consequence they are structurally and universally complete.

Tunable Band‐to‐Band Tunneling and Conducting Path Transition in Local‐Control‐Gate Heterostructure Transistor

AbstractTransition metal dichalcogenide (TMD) material‐based heterostructures have exhibited great potential for building advanced architectures in novel logic devices. A local‐control‐gate (LCG) transistor based on MoTe2/MoS2 heterostructure is fabricated and analyzed, illustrating its tunable electrical characteristics and achieving band‐to‐band tunneling (BTBT) enhancement with an improved peak‐to‐valley current ratio (PVCR) value of 3.04. Compared to the basic dual‐gate tunnel field‐effect transistor (TFET) structure, adding LCG at the bottom not only isolates defect‐induced doping effects from the deposition of top gate dielectrics, but also paves the way for broader applications in multivalued logic and artificial intelligence. Aiming to further verify the operating mechanism of conducting path transition and electrical characteristic trends, commercial technology computer‐aided design (TCAD) is systematically employed assisted by density functional theory (DFT). So that the transition of conducting paths in the heterostructure channel including interlayer quantum effects can be visibly demonstrated while applying various voltages to the LCG. In summary, this work highlights the feasibility of a new LCG structure with tunable electrical characteristics and presents DFT‐assisted TCAD simulations for effective verifications.

Light-Triggered Anti-ambipolar Transistor Based on an In-Plane Lateral Homojunction.

Currently, the construction of anti-ambipolar transistors (AATs) is primarily based on asymmetric heterostructures, which are challenging to fabricate. AATs used for photodetection are accompanied by dark currents that prove difficult to suppress, resulting in reduced sensitivity. This work presents light-triggered AATs based on an in-plane lateral WSe2 homojunction without van der Waals heterostructures. In this device, the WSe2 channel is partially electrically controlled by the back gate due to the screening effect of the bottom electrode, resulting in a homojunction that is dynamically modulated with gate voltage, exhibiting electrostatically reconfigurable and light-triggered anti-ambipolar behaviors. It exhibits high responsivity (188 A/W) and detectivity (8.94 × 1014 Jones) under 635 nm illumination with a low power density of 0.23 μW/cm2, promising a new approach to low-power, high-performance photodetectors. Moreover, the device demonstrates efficient self-driven photodetection. Furthermore, ternary inverters are realized using monolithic WSe2, simplifying the manufacturing of multivalued logic devices.

Note on Partial Falsifiability of Fuzzy and Fuzzy-Extension Hypotheses

In this short note, we adjust the (classical) Falsifiability of a hypothesis that may be 100% true as in classical logic, to the field of multi-valued logics, where there are partialities of truth-value, of indeterminacy, and of false-value of a hypothesis, and we call it Partial Falsifiability.

Ternary logic in the optical controlled-SWAP gate based on Laguerre-Gaussian modes of light

The need set by a computational industry to increase processing power, while simultaneously reducing the energy consumption of data centers, became a challenge for modern computational systems. In this work, we propose an optical communication solution, that could serve as a building block for future computing systems, due to its versatility. The solution arises from Landauer’s principle and utilizes reversible logic, manifested as an optical logical gate with structured light, here represented as Laguerre-Gaussian modes. We introduced a phase-shift-based encoding technique and incorporated multi-valued logic in the form of a ternary numeral system to determine the similarity between two images through the free space communication protocol.

A Mixture of Negative-, Zero-, and Positive-Differential Transconductance Switching from Tellurium/Indium Gallium Zinc Oxide Heterostructures.

Conventional transistors have long emphasized signal modulation and amplification, often sidelining polarity considerations. However, the recent emergence of negative differential transconductance, characterized by a drain current decline during gate voltage sweeping, has illuminated an unconventional path in transistor technology. This phenomenon promises to simplify the implementation of ternary logic circuits and enhance energy efficiency, especially in multivalued logic applications. Our research has culminated in the development of a sophisticated mixed transconductance transistor (M-T device) founded on a precise Te and IGZO heterojunction. The M-T device exhibits a sequence of intriguing phenomena, zero differential transconductance (ZDT), positive differential transconductance (PDT), and negative differential transconductance (NDT) contingent on applied gate voltage. We clarify its operation using a three-segment equivalent circuit model and validate its viability with IGZO TFT, Te TFT, and Te/IGZO TFT components. In a concluding demonstration, the M-T device interconnected with Te TFT achieves a ternary inverter with an intermediate logic state. Remarkably, this configuration seamlessly transitions into a binary inverter when it is exposed to light.