Multithreaded Research Articles

Cooperative scheduling of multi‐core and cloud resources: fine‐grained offloading strategy for multithreaded applications

Nowadays, advanced smart mobile devices equipped with multi-core central processing units for handling multithreaded (MT) applications. However, existing research mainly uses single-thread (ST) computing to deal with applications, which limits the performance of mobile computing. To make full use of multi-core resources, this study proposes a fine-grained MT offloading strategy to solve the offloading problem of MT application. The strategy jointly schedules cloud computing resources, as well as local multi-core computing and communication resources. Precisely, the authors first formulate the minimum energy consumption problem for ST offloading. Then, they prove that the problem is convex and solve it by standard convex optimisation technique. Thirdly, they extend the optimisation goals from ST applications to MT applications, and design calculation rules for MT applications to reduce computing costs. Finally, based on these calculation rules and the optimal solution for ST offloading, they develop a MT offloading strategy to solve the computation offloading problem of MT applications. Simulation results show that the proposed fine-grained MT offloading strategy effectively reduces the minimum delay requirement of mobile computing.

Plagiarism Detection of Multi-Threaded Programs by Mining Behavioral motifs

Plagiarism Detection of Multi-Threaded Programs by Mining Behavioral motifs

Pattern for Using SQL CE Database in Multithreaded Mode Along with C# .NET

Pattern for Using SQL CE Database in Multithreaded Mode Along with C# .NET

BugLoc: Bug Localization in Multi Threaded Application via Graph Mining Approach

Detection of software bugs and its occurrences, repudiation and its root cause is a very difficult process in large multi threaded applications. It is a must for a software developer or software organization to identify bugs in their applications and to remove or overcome them. The application should be protected from malfunctioning. Many of the compilers and Integrated Development Environments are effectively identifying errors and bugs in applications while running or compiling, but they fail in detecting actual cause for the bugs in the running applications. The developer has to reframe or recreate the package with the new one without bugs. It is time consuming and effort is wasted in Software Development Life Cycle.

CMS Full Simulation for Run-2

During LHC shutdown between run-1 and run-2 intensive developments were carried out to improve performance of CMS simulation. For physics improvements migration from Geant4 9.4p03 to Geant4 10.0p02 has been performed. CPU performance has been improved by introduction of the Russian roulette method inside CMS calorimeters, optimization of CMS simulation sub-libraries, and usage of statics build of the simulation executable. As a result of these efforts, CMS simulation has been speeded up by about factor two. In this work we provide description of updates for different software components of CMS simulation. Development of a multi-threaded (MT) simulation approach for CMS will be also discuss.

Multithreaded processors

Multithreaded processors

Parallel Implementation of Texture Based Image Retrieval on The GPU

Most image processing algorithms are inherently parallel, so mu ltithreading processors are suitable in such applications. In huge image databases, image processing takes very long time fo r run on a single core processor because of single thread execution of algorith ms . Graphical Processors Units (GPU) is more co mmon in most image p rocessing applications due to multithread execution of algorith ms, programmab ility and low cost. In this paper we implement texture based image retrieval system in parallel using Co mpute Unified Device Architecture (CUDA) programming model to run on GPU. The main goal of this research work is to parallelize the process of texture based image retrieval through entropy, standard deviation, and local range, also whole process is much faster than normal. Our wo rk uses extensive usage of highly mu ltithreaded architecture of mu lt i-cored GPU. We evaluated the retrieval of the proposed technique using Recall, Precision, and Average Precision measures. Experimental results showed that parallel implementation led to an average speed up of 140.046×over the serial imp lementation. The average Precision and the average Recall of presented method are 39.67% and 55.00% respectively.

On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments

Commercial Off-The-Shelf (COTS) processors are now commonly used in real-time embedded systems. The characteristics of these processors fulfill system requirements in terms of time-to-market, low cost, and high performance-per-watt ratio. However, multithreaded (MT) processors are still not widely used in real-time systems because the timing analysis is too complex. In MT processors, simultaneously-running tasks share and compete for processor resources, so the timing analysis has to estimate the possible impact that the inter-task interferences have on the execution time of the applications. In this paper, we propose a method that quantifies the slowdown that simultaneously-running tasks may experience due to collision in shared processor resources. To that end, we designed benchmarks that stress specific processor resources and we used them to (1) estimate the upper limit of a slowdown that simultaneously-running tasks may experience because of collision in different shared processor resources, and (2) quantify the sensitivity of time-critical applications to collision in these resources. We used the presented method to determine if a given MT processor is a good candidate for systems with timing requirements. We also present a case study in which the method is used to analyze three multithreaded architectures exhibiting different configurations of resource sharing. Finally, we show that measuring the slowdown that real applications experience when simultaneously-running with resource-stressing benchmarks is an important step in measurement-based timing analysis. This information is a base for incremental verification of MT COTS architectures.

Impact of Die-to-Die and Within-Die Parameter Variations on the Clock Frequency and Throughput of Multi-Core Processors

A statistical performance simulator is developed to explore the impact of parameter variations on the maximum clock frequency (FMAX) and throughput distributions of multi-core processors in a future 22 nm technology. The simulator captures the effects of die-to-die (D2D) and within-die (WID) transistor and interconnect parameter variations on critical path delays in a die. A key component of the simulator is an analytical multi-core processor throughput model, which enables computationally efficient and accurate throughput calculations, as compared with cycle-accurate performance simulators, for single-threaded and highly parallel multi-threaded (MT) workloads. Based on microarchitecture designs from previous microprocessors, three multi-core processors with either small, medium, or large cores are projected for the 22 nm technology generation to investigate a range of design options. These three multi-core processors are optimized for maximum throughput within a constant die area. A traditional single-core processor is also scaled to the 22 nm technology to provide a baseline comparison. <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">The salient contributions from this paper are: 1) product-level variation analysis for multi-core processors must focus on throughput, rather than just FMAX, and 2) multi-core processors are more variation tolerant than single-core processors due to the larger impact of memory latency and bandwidth on throughput.</i> To elucidate these two points, statistical simulations indicate that multi-core and single-core processors with an equivalent total core area have similar FMAX distributions (mean degradation of 9% and standard deviation of 5%) for MT applications. In contrast to single-core processors, memory latency and bandwidth constraints significantly limit the throughput dependency on FMAX in multi-core processors, thus reducing the throughput mean degradation and standard deviation by ~50% for the small and medium core designs and by ~30% for the large core design. This improvement in the throughput distribution indicates that multi-core processors could significantly reduce the product design and process development complexities due to parameter variations as compared to single-core processors, enabling faster time to market for high-performance microprocessor products.

Visualizing massively multithreaded applications with ThreadScope

AbstractAs highly parallel multicore machines become commonplace, programs must exhibit more concurrency to exploit the available hardware. Many multithreaded programming models already encourage programmers to create hundreds or thousands of short‐lived threads that interact in complex ways. Programmers need to be able to analyze, tune, and troubleshoot these large‐scale multithreaded programs. To address this problem, we present ThreadScope: a tool for tracing, visualizing, and analyzing massively multithreaded programs. ThreadScope extracts the machine‐independent program structure from execution trace data from a variety of tracing tools and displays it as a graph of dependent execution blocks and memory objects, enabling identification of synchronization and structural problems, even if they did not occur in the traced run. It also uses graph‐based analysis to identify potential problems. We demonstrate the use of ThreadScope to view program structure, memory access patterns, and synchronization problems in three programming environments and seven applications. Copyright © 2009 John Wiley &amp; Sons, Ltd.

A Collaborative Approach for Multi-Threaded SAT Solving

The last decade progresses have led the Satisfiability Problem (SAT) to be a great and competitive practical approach to solve a wide range of industrial and academic problems. Thanks to these progresses, the size and difficulty of the SAT instances has grown significantly. Among the recent solvers, a few are parallel and most of them use the message passing paradigm. In a previous work by Vander-Swalmen et al. (IWOMP, 146-157, 2008), we presented a fine grain parallel SAT solver designed for shared memory using OPENMP and named MTSS, for Multi Threaded Sat Solver. MTSS extends the "guiding path" notion and uses a collaborative approach where a rich thread is in charge of the search-tree evaluation and where a set of poor threads yield logical or heuristics information to simplify the rich task. In this paper, we extend the poor thread abilities of MTSS and present extensive comparative results on random 3-SAT problems. These new experimentations show that fine grained techniques associated to poor tasks within the framework of MTSS can achieve very interesting speedup on multi-core processors.

Single-threaded vs. multi-threaded

Single-threaded vs. multi-threaded

2P2-3F-D3 分散制御用レスポンシブマルチスレッドプロセッサの設計

並列分散制御用Responsive Multi-Threaded (RMT) Processorについて述べる。RMTプロセッサは, 8スレッド同時実行可能な超高性能リアルタイムマルチスレッディングコア, リアルタイム通信リンク(レスポンシブリンク), コンピュータ用I/O, 制御用I/O等を1チップに集積した分散制御用のシステムオンチップである。

Inheritance anomaly in CORBA multithreaded environments

Inheritance anomaly in CORBA multithreaded environments

Solaris Multithreaded programming guide [Book Reviews

Solaris Multithreaded programming guide [Book Reviews

BED: A Multithreaded Kernel for Embedded Systems

Embedded systems tend to be event driven. The BED kernel supports an event-action programming model for an embedded systems development environment called Testbed. The kernel features deterministic scheduling and message transfer services.

Multi-threaded vectorization

Multi-threaded vectorization