Multithreaded System Research Articles

Making Sense of Multi-threaded Application Performance at Scale with NonSequitur

Modern multi-threaded systems are highly complex. This makes their behavior difficult to understand. Developers frequently capture behavior in the form of program traces and then manually inspect these traces. Existing tools, however, fail to scale to traces larger than a million events. In this paper we present an approach to compress multi-threaded traces in order to allow developers to visually explore these traces at scale. Our approach is able to compress traces that contain millions of events down to a few hundred events. We use this approach to design and implement a tool called NonSequitur. We present three case studies which demonstrate how we used NonSequitur to analyze real-world performance issues with Meta's storage engine RocksDB and MongoDB's storage engine WiredTiger, two complex database backends. We also evaluate NonSequitur with 42 participants on traces from RocksDB and WiredTiger. We demonstrate that, in some cases, participants on average scored 11 times higher when performing performance analysis tasks on large execution traces. Additionally, for some performance analysis tasks, the participants spent on average three times longer with other tools than with NonSequitur.

Formula omitted]: A template to build verified thread-local interfaces with software scheduler abstractions

This paper presents ThreadAbs, an extension of the layer-based software formal verification toolkit CCAL (Gu et al., 2018). ThreadAbs is specifically designed to provide better expressiveness and proof management for thread abstraction in multithreaded libraries. Thread abstraction isolates the behavior of each thread from others when providing a top-level formal specification for software. Compared to the original CCAL, ThreadAbs offers significant improvements in this regard.CCAL is a verification framework that enables a layered approach to building certified software, as demonstrated by multiple examples (Gu et al. 2016; Li et al. 2021; Shin et al. 2019). Obviously, its main targets usually include multithread libraries, which support significant improvement in the utilization and isolation of system resources. However, it poses new challenges for formal verification. Firstly, it requires a sudden change in the granularity of concurrency during the implementation and verification of the target software. Typically, systems are associated with software schedulers that are built on top of several underlying components in the system (e.g., thread spawn, yield, sleep, and wake-up). Due to the software scheduler, these systems can be divided into low-level components consisting of modules that the software scheduler depends on (e.g., allocators for shared resources and scheduling queues) and high-level components that use software schedulers (e.g., condition variables, semaphores, and IPCs). Therefore, software formal verification on those systems has to provide proper method to deal with those distinct features, which is usually abstracting other threads’ behavior as much as possible to provide an independent thread model and its formal specification. Secondly, it requires handling side effects from other threads, such as dynamic resource allocation from parents with proper isolation of all threads from each other.CCAL has limited support for two crucial aspects of formal verification in multithreaded systems. Firstly, its previous thread abstraction method does not handle the side effects caused by a parent thread during dynamic initial state allocation properly. Secondly, the proofs produced by CCAL are tied to CertiKOS, which makes it challenging to use them for similar proofs that use CCAL as their verification toolkit. To address these issues, we introduce ThreadAbs, a new mechanized methodology that provides proper thread abstraction to reason about multithreaded programs in conjunction with CCAL. We also extend the previous CertiKOS proof with ThreadAbs to demonstrate its usability and expressiveness.

Write Buffer Partitioning with Rename Register Capping in Multithreaded Cores

In simultaneous multithreaded systems, there are several pipeline resources that are shared amongst multiple threads concurrently. Some of these mutual resources to mention are the register-file and the write buffer. The Physical Register file is a critical shared resource in these types of systems due to the limited number of rename registers available for renaming. The write buffer, another shared resource, is also crucial since it serves as an intermediary between the retirement of a store instruction and the writing of its value to cache. Both components, if not configured accurately, can serve as a bottleneck in inefficient usage of the resources and output undesirable performance. However, when configuring both shared components concurrently, there is potential to all eviate common performance congestion. This paper shows that when implementing a static register capping algorithm (limiting the number of physical register entries for each thread), there is a byproduct of increased variety in source for the write buffer. This also presents an opportunity for the write buffer to have a higher variety to potentially choose for a better suitable thread asit’s source at certain clock cycles. With this presented opportunity, this paper proposes a technique to allow the write buffer to both prioritize and enforce the choice for low-latency threads by partitioning the write buffer in two sections; cache-hit priority and cachehit only partitions, showing that system performance and resource efficiency can be further improved by using this technique in a modified SMT environment.

Practical Implementation of Multithreaded Communication Protocols in Modern Protection Relays

Microprocessor-based protection relays that provide reliable and fast responses to abnormal conditions are of paramount importance to electrical grids. Modern numerical relays constitute communication protocols to facilitate data exchange among protection devices. Though it has become an integral part of electrical substation devices, there has not been any significant article that puts forth a detailed description of the preemptive multithreading implementation of multiple communication protocols for protection relays. Hence, this article is aimed at designing a preemptive multithreading system comprising IEC 61850 Manufacturing Message Specification (MMS), Generic Object-Oriented Substation Event (GOOSE), and Sampled Values (SV) along with Modbus TCP/IP and IEC 60870-5-104 communication protocols for protection relays. Latest products from prominent manufacturers of protection relays adopt preemptive multithreading on a real-time Linux operating system. In this work, the designed multi-protocol communication system is implemented on a real-time embedded Linux-based cortex-A7 core of the STM32MP157D-DK1 device. The designed system is verified by conducting an interoperability test with ABB REF615 and Thytronic NA11 protection relays.

A Real-Time Sorting Robot System for Panax Notoginseng Taproots Equipped with an Improved Deeplabv3+ Model

The classification of the taproots of Panax notoginseng is conducive to improving the economic added value of its products. In this study, a real-time sorting robot system for Panax notoginseng taproots was developed based on the improved DeepLabv3+ model. The system is equipped with the improved DeepLabv3+ classification model for different grades of Panax notoginseng taproots. The model uses Xception as the taproot feature extraction network of Panax notoginseng. In the residual structure of the Xception network, a group normalization layer with deep separable convolution is adopted. Meanwhile, the global maximum pooling method is added in the Atrous Spatial Pyramid Pooling (ASPP) part to retain more texture information, and multiple shallow effective feature layers are designed to overlap in the decoding part to minimize the loss of features and improve the segmentation accuracy of Panax notoginseng taproots of all grades. The model test results show that the Xception-DeepLabv3+ model performs better than VGG16-U-Net and ResNet50-PSPNet models, with a Mean Pixel Accuracy (MPA) and a Mean Intersection over Union (MIoU) of 78.98% and 88.98% on the test set, respectively. The improved I-Xce-DeepLabv3+ model achieves an average detection time of 0.22 s, an MPA of 85.72%, and an MIoU of 90.32%, and it outperforms Xce-U-Net, Xce-PSPNet, and Xce-DeepLabv3+ models. The system control software was developed as a multi-threaded system to design a system grading strategy, which solves the problem that the identification signal is not synchronized with the grading signal. The system test results show that the average sorting accuracy of the system is 77% and the average false detection rate is 21.97% when the conveyor belt running speed is 1.55 m/s. The separation efficiency for a single-channel system is 200–300 kg/h, which can replace the manual work of three workers. The proposed method meets the requirements of current Panax notoginseng processing enterprises and provides technical support for the intelligent separation of Panax notoginseng taproots.

Синтез оптической нейроморфной структуры с функциональным разделением нейронов для распределения потоков информации

The work presents analysis of possible application of self-generating neural networks, which can independently generate a topological map of neuron connections while modelling biological neurogenesis, in multi-threaded information communication systems. A basic optical neural network cell is designed on the basis of the applied layered composition performing data processing. A map of neuron connections represents not an ordered structure providing a regular graph for exchange of information between neurons, but a set of cognitive reserve represented as an unconnected set of neuromorphic cells. Modelling of neuron death (apoptosis) and creation of dendrite-axon connections makes it possible to implement a stepwise neural network growth algorithm. Despite challenges in implementing this process, creating a growing network in an optical neural network framework solves the problem of initial forming of the neural network architecture, which greatly simplifies the learning process. Neural network cells used with the network growth algorithm resulted in neural network structures that use internal self-sustaining rhythmic activity to process information. This activity is a result of spontaneously formed closed neural circuits with common neurons among neuronal cells. Such organisation of recirculation memory leads to solutions with reference to such intra-network activity. As a result, response of the network is determined not only by stimuli, but also by the internal state of the network and its rhythmic activity. Network functioning is affected by internal rhythms, which depend on the information passing through the neuron clusters, which results in formation of a specific rhythmic memory. This can be used for tasks that require solutions to be worked out based on certain parameters, but they shall be unreproducible when the network is repeatedly stimulated by the same influences. Such tasks include ensuring information transmission security when using some set of carriers. The task of determining a number of frequencies and their frequency plan depends on external factors. To exclude possible repeating generation of the same carrier allocation, it is necessary to use networks of the configuration under consideration that can influence generation of solutions through the gathered experience.

Extending the wait-free hierarchy to multi-threaded systems

In modern operating systems and programming languages adapted to multicore computer architectures, parallelism is abstracted by the notion of execution threads. Multi-threaded systems have two major specificities: on the one part, new threads can be created dynamically at runtime, so there is no bound on the number of threads participating in long-running executions. On the other part, threads have access to a memory allocation mechanism that cannot allocate infinite arrays. These specificities make it challenging to adapt some algorithms to multi-threaded systems, in particular those that need to assign one shared register per process. This paper explores the synchronization power of shared objects in multi-threaded systems by extending the famous Herlihy’s wait-free hierarchy to take these constraints into consideration. It proposes to subdivide the set of objects with an infinite consensus number into nine new degrees, depending on their ability to synchronize a bounded, finite or infinite number of processes, with or without the need to allocate an infinite array. To show the relevance of the proposed extension, for each new degree it is either proved that it is empty, or an object illustrating it is proposed.

DITIS: A Distributed Tiered Storage Simulator

This paper presents DITIS, a simulator for distributed and tiered file-based storage systems. In particular, DITIS can model a distributed storage system with up to three levels of storage tiers and up to three additional levels of caches. Each tier and cache can be configured with different number and type of storage media devices (e.g., HDD, SSD, NVRAM, DRAM), each with their own performance characteristics. The simulator utilizes the provided characteristics in fine-grained performance cost models (which are distinct for each device type) in order to compute the duration time of each I/O request processed on each tier. At the same time, DITIS simulates the overall flow of requests through the different layers and storage nodes of the system using numerous pluggable policies that control every aspect of execution, ranging from request routing and data redundancy to cache and tiering strategies. For performing the simulation, DITIS adapts an extended version of the Actor Model, during which key components of the system exchange asynchronous messages with each other, much like a real distributed multi-threaded system. The ability to simulate the execution of a workload in such an accurate and realistic way brings multiple benefits for its users, since DITIS can be used to better understand the behavior of the underlying file system as well as evaluate different storage setups and policies.

Matrix Method for Modelling of Multicomponent and Multistream Energy Systems and Installations of Thermal Power Plants

The aim of this work is to increase the operational efficiency of the multicomponent multithreaded power units and systems of the TPP using modeling, calculation and optimization. The goal is achieved by solving the following tasks: development of the tasks’ classification system and a unified methodology for the mathematical description of energy formation and mass flows’ processes in multicomponent and multithreaded power units of the TPP; development of a model of a steam turbine power unit; development of a model of heat and mass transfer processes in multi-stage multistream multiphase systems. The most significant results obtained were: the developed unified methodology for the matrix description of the processes of energy and mass flows’ formation in multicomponent multistream energy systems of the TPP. Within the framework of the proposed methodology, a model of a steam turbine power was developed; model solutions were obtained and analyzed in order to calculate the energy characteristics of a heating turbine unit, the reliability and validity of the proposed approach was shown, a mathematical model of multistream multi-stage heat exchange systems were developed. The significance of the results obtained consisted in the development of a simple but informative mathematical model of a thermal power plant turbine generator and a model of multistream multi-stage heat exchange systems, each stage of which can have an arbitrary number of input and output flows with a possible phase transition in heat carriers.ave an arbitrary number of input and output flows with a possible phase transition in heat carriers.

Distributed Architecture for an Integrated Development Environment, Large Trace Analysis, and Visualization.

Integrated development environments (IDEs) provide many useful tools such as a code editor, a compiler, and a debugger for creating software. These tools are highly sophisticated, and their development requires a significant effort. Traditionally, an IDE supports different programming languages via plugins that are not usually reusable in other IDEs. Given the high complexity and constant evolution of popular programming languages, such as C++ and even Java, the effort to update those plugins has become unbearable. Thus, recent work aims to modularize IDEs and reuse the existing parser implementation directly in compilers. However, when IDE debugging tools are insufficient at detecting performance defects in large and multithreaded systems, developers must use tracing and trace visualization tools in their software development process. Those tools are often standalone applications and do not interoperate with the new modular IDEs, thus losing the power and the benefits of many features provided by the IDE. The structure and use cases of tracing tools, with the potentially massive execution traces, significantly differ from the other tools in IDEs. Thus, it is a considerable challenge, one which has not been addressed previously, to integrate them into the new modular IDEs. In this paper, we propose an efficient modular client–server architecture for trace analysis and visualization that solves those problems. The proposed architecture is well suited for performance analysis on Internet of Things (IoT) devices, where resource limitations often prohibit data collection, processing, and visualization all on the same device. The experimental evaluation demonstrated that our proposed flexible and reusable solution is scalable and has a small acceptable performance overhead compared to the standalone approach.

Research of a multithreaded non-deterministic system model

Managing the systems which behaviour is non-deterministic is one of the most important problems in modern management theory. Today, systems with structural and behavioural complexity are prevalent in all areas of human activity, and therefore, their research is of the utmost importance. Such systems, as opposed to deterministic systems, are called non-deterministic. They are characterised by difficult predictable behaviour determined both by external random influences, and within the systems themselves. A clear example of a non-deterministic system is crowds of people, factories, and computer networks and systems. The problem of non-deterministic behaviour directly within the context of professional activities can be seen using an example of building syntactic analysers. The aim of the paper is to design a class of systems oriented towards supporting elements of a discrete event model. The target of research is to simulate discrete event models. The subject of research is a creation of a discrete event model based on the behaviour of an undetermined finite state automaton. During the preparation of the paper, there was developed and practically implemented an algorithm for the application, which materializes the principle of working with threads. The results obtained in the paper are aimed at solving the problem of parallel data processing based on the parallelism of NFA's (non-deterministic finite automaton) behaviour when reading the input string characters. As a result, this should have a positive impact on the regulation of the simulation processes of a non-deterministic system, increasing its efficiency and stability. In conclusion, the algorithm of the application work is disclosed and conclusions about the effectiveness and efficiency of its development are drawn.

Benchmarking learned indexes

Recent advancements in learned index structures propose replacing existing index structures, like B-Trees, with approximate learned models. In this work, we present a unified benchmark that compares well-tuned implementations of three learned index structures against several state-of-the-art "traditional" baselines. Using four real-world datasets, we demonstrate that learned index structures can indeed outperform non-learned indexes in read-only in-memory workloads over a dense array. We investigate the impact of caching, pipelining, dataset size, and key size. We study the performance profile of learned index structures, and build an explanation for why learned models achieve such good performance. Finally, we investigate other important properties of learned index structures, such as their performance in multi-threaded systems and their build times.

Novel prioritized LRU circuits for shared cache in computer systems

Cache sharing technique is critical in multi-core and multi-threading systems. It potentially delays the execution of real-time applications and makes the prediction of the worst-case execution time (WCET) of real-time applications more challenging. Prioritized cache has been demonstrated as a promising approach to address this challenge. Instead of the conventional prioritized cache schemes realized at the architecture level by using cache controllers, this work presents two prioritized least recently used (LRU) cache replacement circuits that directly accomplish the prioritization inside the cache circuits, hence significantly reduces the cache access latency. The performance, hardware and power overheads due to the proposed prioritized LRU circuits are investigated based on a 65 nm CMOS technology. It shows that the proposed circuits have very low overhead compared to conventional cache circuits. The presented techniques will lead to more effective prioritized shared cache implementations and benefit the development of high-performance real-time systems.

Sthread: In-Vivo Model Checking of Multithreaded Programs

This work strives to make formal verification of POSIX multithreaded programs easily accessible to general programmers. Sthread operates directly on multithreaded C/C++ programs, without the need for an intermediate formal model. Sthread is in-vivo in that it provides a drop-in replacement for the pthread library, and operates directly on the compiled target executable and application libraries. There is no compiler-generated intermediate representation. The system calls in the application remain unaltered. Optionally, the programmer can add a small amount of additional native C code to include assertions based on the user's algorithm, declarations of shared memory regions, and progress/liveness conditions. The work has two important motivations: (i) It can be used to verify correctness of a concurrent algorithm being implemented with multithreading; and (ii) it can also be used pedagogically to provide immediate feedback to students learning either to employ POSIX threads system calls or to implement multithreaded algorithms. This work represents the first example of in-vivo model checking operating directly on the standard multithreaded executable and its libraries, without the aid of a compiler-generated intermediate representation. Sthread leverages the open-source SimGrid libraries, and will eventually be integrated into SimGrid. Sthread employs a non-preemptive model in which thread context switches occur only at multithreaded system calls (e.g., mutex, semaphore) or before accesses to shared memory regions. The emphasis is on finding "algorithmic bugs" (bugs in an original algorithm, implemented as POSIX threads and shared memory regions. This work is in contrast to Context-Bounded Analysis (CBA), which assumes a preemptive model for threads, and emphasizes implementation bugs such as buffer overruns and write-after-free for memory allocation. In particular, the Sthread in-vivo approach has strong future potential for pedagogy, by providing immediate feedback to students who are first learning the correct use of Pthreads system calls in implementation of concurrent algorithms based on multithreading.

The parallel approach to issue of operational management optimization problem on transport gateway system

The universal parallelization software shell for joint data processing, implemented in combination with a distributed computing system, is considered. The research purpose – to find the most effective solution for the navigable canal management information system organizing. One optimization option is to increase computer devices computing power by combining them into a single computing cluster. The management optimizing task of a locked shipping channel for execution to adapt in a multi-threaded environment is proposed with constraints on a technologically feasible schedule. In article shows algorithms and gives recommendations for their application in the subtasks formation in parallel processing case, as well as on a separate thread. The proposed approach to building a tree of options allows you to optimally distribute the load between all resources multi-threaded system any structure.

SGXPool: Improving the performance of enclave creation in the cloud

AbstractDeploying user data or programs in cloud risks divulging their privacy because the cloud‐side supervisors, such as system administrators, can leverage the higher privilege to snoop the user data. Based on the trusted execution environment (TEE) technology, Intel Software Guard eXtension (SGX) is a practical remedy to user privacy, which employs hardware‐assisted enclave to wrap the sensitive data, preventing them from the disclosure. However, the application performance is hurt due to the CPU‐expensive and frequent operations on the enclave creation and destruction. In this paper, we propose SGXPool, an application‐level framework of resource management to relieve the above issue. SGXPool first uses a preallocated resource pool to assign/revoke the enclave on demand and avoids its cost of dynamical creation and destruction. Then, SGXPool utilizes another resource pool to constrain the threading overhead such as thread initialization, scheduling, and destruction. In addition, SGXPool exposes the simple and clear interface, allowing users or programmers to apply SGXPool without any intrusive modifications on the original SGX application. We implement SGXPool in the typical web servers which use the multithreading to handle the concurrent user requests. The evaluation results show that SGXPool can improve the performance of the original multithreading system up to 19 times. Meanwhile, the original security of SGX is maintained.

Measurement applications in Industry 4.0: the case of an IoT–oriented platform for remote programming of automatic test equipment

<p><span lang="EN-GB">A laboratory regarded as a site that collects IoT devices, and which allows remote clients to use them as an automatic test equipment (ATE) through a controller acting as service provider, is proposed herein. To assure efficiency and responsiveness, the controller is programmed as a multithreading system that takes advantage of multicore processors. The controller includes a server application that supports communication with clients by means of a TCP/IP protocol. It uses GPIB bus functionalities to control the instruments of the local ATE. It allows several clients to connect and interact with the specific resources of the laboratory. Thanks to the availability of identical sets of resources and to the underlying multithreading philosophy, client requests are processed in tandem rather than according to a classical queuing approach.</span></p><p><span lang="EN-GB"><br /></span></p>

Parallel Ant Colony Algorithm for Shortest Path Problem

During travelling, more and more information must be taken into account, and travelers have to make several complex decisions. In order to support these decisions, IT solutions are unavoidable, and as the computational demand is constantly growing, the examination of state-of-the-art methodologies is necessary. In our research, a parallelized Ant Colony algorithm was investigated, and a parameter study on a real network has been made. The aim was to inspect the sensibility of the method and to demonstrate its applicability in a multi-threaded system (e.g. Cloud-based systems). Based on the research, increased effectiveness can be reached by using more threads. The novelty of the paper is the usage of the processors’ parallel computing capability for routing with the Ant Colony algorithm.

System performance enhancement with thread suspension for simultaneous multi-threading processors

ABSTRACT Simultaneous Multi-Threading systems improve performance by allowing multiple independent threads to be executed concurrently with shared key resources. Unfair sharing of resources among multiple threads can easily clog the pipeline stages by slower threads and hamper the normal processing of faster threads. In this paper, we propose a thread-suspension scheme combined with a uniform register file capping technique to avoid imbalanced distribution of resources. When a shared resource congestion occurs on the pipeline stages, the thread with the lowest resource utilization efficiency among all active threads will be suspended so as to provide other threads more space to proceed for a higher throughput. Our experimental results show that our proposed technique improves the average system throughput in terms of Instruction Per Clock Cycle by up to 51.3%, with little compromise in execution fairness.

Robust Multithreaded Object Tracker through Occlusions for Spatial Augmented Reality

A spatial augmented reality (SAR) system enables a virtual image to be projected onto the surface of a real-world object and the user to intuitively control the image using a tangible interface. However, occlusions frequently occur, such as a sudden change in the lighting environment or the generation of obstacles. We propose a robust object tracker based on a multithreaded system, which can track an object robustly through occlusions. Our multithreaded tracker is divided into two threads: the detection thread detects distinctive features in a frame-to-frame manner, and the tracking thread tracks features periodically using an optical-flow-based tracking method. Consequently, although the speed of the detection thread is considerably slow, we achieve real-time performance owing to the multithreaded configuration. Moreover, the proposed outlier filtering automatically updates a random sample consensus distance threshold for eliminating outliers according to environmental changes. Experimental results show that our approach tracks an object robustly in real-time in an SAR environment where there are frequent occlusions occurring from augmented projection images.