Write Buffer Partitioning with Rename Register Capping in Multithreaded Cores

Abstract

In simultaneous multithreaded systems, there are several pipeline resources that are shared amongst multiple threads concurrently. Some of these mutual resources to mention are the register-file and the write buffer. The Physical Register file is a critical shared resource in these types of systems due to the limited number of rename registers available for renaming. The write buffer, another shared resource, is also crucial since it serves as an intermediary between the retirement of a store instruction and the writing of its value to cache. Both components, if not configured accurately, can serve as a bottleneck in inefficient usage of the resources and output undesirable performance. However, when configuring both shared components concurrently, there is potential to all eviate common performance congestion. This paper shows that when implementing a static register capping algorithm (limiting the number of physical register entries for each thread), there is a byproduct of increased variety in source for the write buffer. This also presents an opportunity for the write buffer to have a higher variety to potentially choose for a better suitable thread asit’s source at certain clock cycles. With this presented opportunity, this paper proposes a technique to allow the write buffer to both prioritize and enforce the choice for low-latency threads by partitioning the write buffer in two sections; cache-hit priority and cachehit only partitions, showing that system performance and resource efficiency can be further improved by using this technique in a modified SMT environment.