Multithreaded Processor Research Articles

Design of High performance and Low power Simultaneous Multi-Threaded Processor

In this paper, we present the design of a High Performance Multi-Threaded Processor. Processing of high quality images is inevitable in applications such as, HD TV, Gaming Multimedia, etc. which require a great processing power with low power consumption. This can be achived with multi-threaded processors which optimally utilises the Functional Units (Fus). The speed of processing is as good as multi-core processors with lesser area. A conflict resolver (CR) is designed for scheduling the instructions, which involves allocation of Fu. The data move instructions are in majority in any of the programs; the corresponding logic blocks are replicated and speed of execution is further improved. We illustrated for two-threaded processorHowever, it is possible to extend the design for any number of threads by suitably redesigning the CR, and also replicate Transfer Logic and CPU Registers. DOI: http://dx.doi.org/10.11591/ijece.v3i3.2530

Dynamic power dissipation control method for real-time processors based on hardware multithreading

In order to eliminate the energy waste caused by the traditional static hardware multithreaded processor used in real-time embedded system working in the low workload situation, the energy efficiency of the hardware multithread is discussed and a novel dynamic multithreaded architecture is proposed. The proposed architecture saves the energy wasted by removing idle threads without manipulation on the original architecture, fulfills a seamless switching mechanism which protects active threads and avoids pipeline stall during power mode switching. The report of an implemented dynamic multithreaded processor with 45 nm process from synthesis tool indicates that the area of dynamic multithreaded architecture is only 2.27% higher than the static one in achieving dynamic power dissipation, and consumes 1.3% more power in the same peak performance.

Predicting Architectural Vulnerability on Multithreaded Processors under Resource Contention and Sharing

Architectural vulnerability factor (AVF) characterizes a processor's vulnerability to soft errors. Interthread resource contention and sharing on a multithreaded processor (e.g., SMT, CMP) shows nonuniform impact on a program's AVF when it is co-scheduled with different programs. However, measuring the AVF is extremely expensive in terms of hardware and computation. This paper proposes a scalable two-level predictive mechanism capable of predicting a program's AVF on a SMT/CMP architecture from easily measured metrics. Essentially, the first-level model correlates the AVF in a contention-free environment with important performance metrics and the processor configuration, while the second-level model captures the interthread resource contention and sharing via processor structures' occupancies. By utilizing the proposed scheme, we can accurately estimate any unseen program's soft error vulnerability under resource contention and sharing with any other program(s), on an arbitrarily configured multithreaded processor. In practice, the proposed model can be used to find soft error resilient thread-to-core scheduling for multithreaded processors.

A fast, free-form rubber-sheet algorithm for contiguous area cartograms

This article presents a fast, free-form rubber-sheet (Carto3F) algorithm for the construction of contiguous area cartograms. Rubber-sheet algorithms are influential and popular because of their conceptual simplicity. Existing rubber-sheet algorithms, however, tend to be algorithmically inefficient and computationally slow. More critically, they cannot completely preserve topology. Carto3F specifically improves rubber-sheet algorithms in these two aspects. First, with a spatial structure of quadtree and a mathematical condition for topological equivalence, Carto3F can prevent topological errors and guarantees topological integrity. Second, Carto3F is designed with efficiency as a priority. Its efficiency is primarily gained through using the auxiliary quadtree to reduce the number of points to be transformed. Furthermore, Carto3F allows parallel computation and can fully take advantage of the increasingly common multi-core, multi-thread processors. Based on the mathematical analysis, Carto3F also mitigates the effect of force cancellation that is inherent in rubber-sheet algorithms. On a computer equipped with a 2.4-GHz quad-core CPU, Carto3F can produce quality population cartograms of the United States, China, and the world within 1 second, 18 seconds, and 8 minutes, respectively. Quantitative measures show that Carto3F outperforms the optimized rubber-sheet algorithm and the diffusion algorithm in both transformation effectiveness and computational efficiency.

Linux Support for Fast Transparent General Purpose Checkpoint/Restart of Multithreaded Processes in Loadable Kernel Module

Checkpoint/Restart is the ability to save the state of a running application so that it can later resume its execution from the time of the checkpoint. These are techniques with many potential applications, including establishment of a fault-tolerant environment, improving system resource utilization, and true migration of a process. With increasing hardware speed and size of clusters the average time between failures has been reduced. Therefore, fault tolerance and ability to checkpoint a process have become inevitable. Almost all platforms deployed for high-performance computing support process checkpoint/restart. Linux as one of the popular operating systems does not provide a general purpose implementation. Some are limited to specific type of parallel programming library, confined to some unique well-behaved type of applications, or reliant on specific features in kernel which could be missing on many occasions. Most of implementations demand elaborate practice of recompiling a whole kernel to apply required patches. In this paper, we describe the design and implementation of multithreaded process checkpoint/restart system for Linux which provide capability of dynamic extension to increase compatibility and reduce system overhead. It does not impose any requirement on the existence of a special facility in the operating system and can do checkpoint/restart of an application independent of their behavior and fully transparent. The entire system is absolutely implemented in multiple kernel loadable modules, which result in ease of use and eliminate the burden of complex system administration.

New Educational Approach to Direct Experience through Embedded System Design and Implementation

Direct experience is necessary in the information age, where virtual and indirect experiences are becoming increasingly common. Designing and implementing embedded systems give innovative, effective, and importantly, direct experience to students of computer science and information technology. Communicating sequential processes (CSP), which are effectively implemented by an event-driven and multi-thread processor, have an advantage in understanding the design and implementation of an embedded system because design concepts are implemented in a natural way. We propose a new educational approach, in which a formal development method called incrementally modular abstraction hierarchy (IMAH) is employed. As an example, a line-tracing car is designed and implemented using IMAH. 

High Performance Color Image Processing in Multicore CPU using MFC Multithreading

Image processing is an engineering field where stored image data is readily available for parallel processing. Basically data processing algorithms developed in sequential approach are not capable of harnessing the computing power of individual cores present in a single-chip multicore processor. To utilize the multicore processor efficiently on windows platform for color image processing applications, a lock-free multithreading approach was developed using Visual C++ with Microsoft Foundation Class (MFC) support. This approach distributes the image data processing task on multicore Central Processing Unit (CPU) without using parallel programming framework like Open Multi-Processing (OpenMP) and reduces the algorithm execution time. In image processing, each pixel is processed using same set of high-level instruction which is time consuming. Therefore to increase the processing speed of the algorithm in a multicore CPU, the entire image data is partitioned into equal blocks and copy of the algorithm is applied on each block using separate worker thread. In this paper, multithreaded color image processing algorithms namely contrast enhancement using fuzzy technique and edge detection were implemented. Both the algorithms were tested on an Intel Core i5 Quad-core processor for ten different images of varying pixel size and their performance results are presented. A maximum of 71% computing performance improvement and speedup of about 3.4 times over sequential approach was obtained for large-size images using four thread model.

Low-cost and power-efficient thread collision detection scheme for shared caches in a real-time multithreaded embedded processor

This paper addresses an important issue in a real-time multithreaded embedded processor where several active hardware threads share the critical resources such as caches in the processor. Thread interferences or collisions could lead to severe performance degradations on the real-time threads. Although the cache interference issue on real-time multithreaded processors has been studied before, no cost-effective and simpler hardware solutions were proposed to maintain the single thread performance of the real-time thread while still letting the low-priority threads progress. A novel technique called collision tag is proposed to address these issues. Progressively, the collision tag scheme can be reduced into a more power-efficient form called collision bit vector, with almost no impact in the overall performance of the real-time multithreaded embedded processor.

An effective cache scheduling scheme for improving the performance in multi-threaded processors

Abstract Although in a multi-threaded processor, the processor may execute more than one process simultaneously to maximize the overall throughput of the system, the executing processes may compete with each other in using shared caches of the processor. This can seriously affect the average performance of the processes as the probability of cache hit for each process could be lowered. In this paper, we propose a new algorithm called the sharable cache partitioning algorithm (ShaParti), for scheduling the processor caches amongst co-running processes. In ShaParti, each executing process has its own cache and a priority scheme is designed for them to share the caches belonging to other executing processes. The performance goals of ShaParti are to improve the cache hit rates of the processes and at the same time the cache miss rates of other concurrent processes will not be lowered compared with the case in which each process has its own cache. Extensive experiments have been performed to illustrate the effectiveness of ShaParti in improving the performance in accessing shared processor caches.

An efficient method for detecting concurrency errors in object-oriented programs

Multicore and multi-threaded processors have become the norm for modern processors. Accordingly, concurrent programs have become more and more prevalent despite being difficult to write and understand. Although errors are highly likely to appear in concurrent code, conventional error detection methods such as model checking, theorem proving, and code analysis do not scale smoothly to concurrent programs. Testing is an indispensable technique for detecting concurrency errors, but it involves a great deal of manual work and is inefficient. This paper presents an automatic method for detecting concurrency errors in classes in object-oriented languages. The method uses a heuristic algorithm to automatically generate test cases that can effectively trigger errors. Then, each test case is executed automatically and a fast method is adopted to identify the actual concurrency error from anomalous run results. We have implemented a prototype of the method and applied it to some typical Java classes. Evaluation shows that our method is more effective and faster than previous work.

Protection Structures in Multithreaded Systems

We consider a single-address-space system which implements a form of segmentation with paging within the framework of the multithreaded model of program execution. A salient problem of a system of this type is the definition of the set of mechanisms enforcing memory protection. We present a paradigm for the protection system design that is based on the well-known concepts of protection domains and access rights. The resulting environment guarantees an effective separation of the memory resources of the different processes, whose loosely coupled interactions correspond to explicit actions of information sharing. Within the boundaries of a single multithreaded process, a less-stringent protection requirement is to confine the consequences of a programming error in the thread that originated the error. These results are obtained by taking advantage of techniques of symmetric-key cryptography to represent access privileges in memory at the level of the single pages that form a segment.

The Dependable Responsive Multithreaded Processor for Distributed Real-Time Systems

This article illustrates the design and implementation of the Dependable Responsive Multithreaded Processor (D-RMTP) for distributed real-time systems, especially humanoid robots. Paper presents a humanoid robot Kojiro. Kojiro's controllers are currently implemented by using the 16-bit H8 microprocessor with a USB network. We are planning to replace them with the D-RMTPs with responsive link network to improve dependability, so that the small controllers with the D-RMTPs are embedded at every joint of the robot and are interconnected via a real-time network called responsive link for distributed control. Therefore, the D-RMTP is designed to meet severe requirements in terms of footprint, latency, scalability, and dependability. The dependable responsive multithreaded processor (D-RMTP) applies priority-based control to all computation and communication levels. it also implements a hardware-based logging mechanism and errorcorrecting code (ECC) for improving dependability. the system on a chip (SOC), memory modules, and thermal and voltage sensors are integrated into the system in a package (SIP).

The XMOS Architecture and XS1 Chips

The XMOS architecture scales from real-time systems with a single multithreaded processor to systems with thousands of processors. Concurrent processing, communications, and I/O are supported by the instruction set of the XCORE processors and by the message-routing techniques and protocols in the XMOS interconnect. The event-driven architecture supports energy-efficient multicore and multichip systems in which cores are active only when needed.

Root locus analysis and design of the adaptation process in active noise control

This paper applies root locus theory to develop a graphical tool for the analysis and design of adaptive active noise control systems. It is shown that the poles of the adaptation process performed in these systems move on typical trajectories in the z-plane as the adaptation step-size varies. Based on this finding, the dominant root of the adaptation process and its trajectory can be determined. The first contribution of this paper is formulating parameters of the adaptation process root locus. The next contribution is introducing a mechanism for modifying the trajectory of the dominant root in the root locus. This mechanism creates a single open loop zero in the original root locus. It is shown that appropriate localization of this zero can cause the dominant root of the locus to be pushed toward the origin, and thereby the adaptation process becomes faster. The validity of the theoretical findings is confirmed in an experimental setup which is implemented using real-time multi-threading and multi-core processing techniques.

재해 복구를 위한 백업 시스템의 안정성 검증

시스템의 장애와 재해로부터 기업의 자산을 보호하는 것은 IT 운영 관리자들이 가장 고려해야 할 사항들 중 하나이다. 그러므로 본 연구는 이러한 재해 복구를 위한 백업 시스템을 제안하였다. 기존의 백업 방식이 데이터베이스의 업데이트가 발생하면 그 이력이 개장 기록(redo log) 파일에 저장이 되고 이 기록파일이 예정된 파일의 크기를 넘어서면 순차적으로 기록보관소 기록(archive log) 파일들로 저장된다. 그러므로 데이터베이스의 변경이 생기는 동안 실시간 변경되는 데이터를 백업받는 과정에 데이터 손실의 오류가 발생할 수 있다. 제안한 백업 시스템은 온라인 개장 기록을 처리기록(transaction log) 데이터베이스로 실시간 백업하고, 기존 백업방법에서 누락 될 수 있는 자료보관소 기록(archive log)으로 백업된다. 그러므로 데이터의 복구 시 온라인으로 개장 기록까지 실시간 복구가 가능하여 데이터의 손실을 최소화 할 수 있을 뿐만 아니라, 멀티스레드 처리방법으로 데이터 복제가 수행되어 시스템의 성능도 향상 시킬 수 있도록 설계하였다. 설계된 백업 시스템의 안정성을 검증하기 위하여 CPN(Coloured Petri Nets)을 도입 하였으며, 백업시스템의 각 수행 단계는 CPN의 그래픽으로 도식화 하고, CPN의 정의와 정리를 기반으로 안정성을 검증하였다.

Development of Java multi-threaded simulation for chemical reacting flow of ethanol

Multi-threading in Java enhances computational performance and facilitates the development of parallel software. To obtain high performance on multi-core systems, this study develops a multi-threaded simulation code using Java for the chemical reacting flow of ethanol. Three ethanol reaction models were implemented in this code to investigate the effects of multi-threaded processing on three multi-core CPUs. The computational load for the chemical reaction significantly increases with the number of chemical equations and high temperature portion of the domain. To enhance parallel performance, the domain in which the chemical reaction occurs is appropriately decomposed at each time step, resulting in improved parallel performance.

Adaptive instruction dispatching techniques for Simultaneous Multi-Threading (SMT) processors

Simultaneous Multi-Threading (SMT) provides a technique to improve resource utilization ability by sharing key data-path components among multiple independent threads. When critical resources are shared by multiple threads, effective use of these resources proves to be the most important factor in fully exploiting the system potential. Transient behaviors of various threads in terms of their execution parallelism can easily affect utilization efficiency of these shared resources. To commit more resources to threads that are more active allows for better resource utilization and thus higher throughput. In this paper, we propose a real-time dynamic scheduler for the SMT which dispatches instructions from threads based on thread-activeness information gathered in real time and dynamically adjusts dispatching priorities among threads accordingly. An extensive simulation shows a significant gain in system throughput by this technique. The performance of the proposed dispatching technique is evaluated on different workload mixtures created based on instruction-level parallelism available in each thread. An average of 6.5% and maximum of 15% performance improvement is observed with the proposed dispatching technique.

FPGA-based reconfigurable processor for ultrafast interlaced ultrasound and photoacoustic imaging

In this paper, we report, to the best of our knowledge, a unique field-programmable gate array (FPGA)-based reconfigurable processor for real-time interlaced co-registered ultrasound and photoacoustic imaging and its application in imaging tumor dynamic response. The FPGA is used to control, acquire, store, delay-and-sum, and transfer the data for real-time co-registered imaging. The FPGA controls the ultrasound transmission and ultrasound and photoacoustic data acquisition process of a customized 16-channel module that contains all of the necessary analog and digital circuits. The 16-channel module is one of multiple modules plugged into a motherboard; their beamformed outputs are made available for a digital signal processor (DSP) to access using an external memory interface (EMIF). The FPGA performs a key role through ultrafast reconfiguration and adaptation of its structure to allow real-time switching between the two imaging modes, including transmission control, laser synchronization, internal memory structure, beamforming, and EMIF structure and memory size. It performs another role by parallel accessing of internal memories and multi-thread processing to reduce the transfer of data and the processing load on the DSP. Furthermore, because the laser will be pulsing even during ultrasound pulse-echo acquisition, the FPGA ensures that the laser pulses are far enough from the pulse-echo acquisitions by appropriate time-division multiplexing (TDM). A co-registered ultrasound and photoacoustic imaging system consisting of four FPGA modules (64-channels) is constructed, and its performance is demonstrated using phantom targets and in vivo mouse tumor models.

Large-scale time-harmonic electromagnetic field analysis using a multigrid solver on a distributed memory parallel computer

This paper reports on an investigation into large-scale parallel time-harmonic electromagnetic field analysis based on the finite element method. The parallel geometric multigrid preconditioned iterative solver for the resulting linear system was developed on a cluster of shared memory parallel computers. We propose a hybrid parallel ordering method for the parallelization of a multiplicative Schwarz smoother, which is a key component of the multigrid solver for electromagnetic field analysis. The method, using domain decomposition ordering for multi-process parallelism and introducing block multi-color ordering for multi-thread parallel processing, attains a high convergence rate with a small number of message passing interface communications and thread synchronizations. The numerical test confirms that the proposed method attains a solver performance more than twice as good as the conventional method based on multi-color ordering. Furthermore, an approximately 800 million degrees of freedom problem is successfully solved on 256 quad-core processors.

Probabilistic modeling for job symbiosis scheduling on SMT processors

Symbiotic job scheduling improves simultaneous multithreading (SMT) processor performance by coscheduling jobs that have “compatible” demands on the processor's shared resources. Existing approaches however require a sampling phase, evaluate a limited number of possible coschedules, use heuristics to gauge symbiosis, are rigid in their optimization target, and do not preserve system-level priorities/shares. This article proposes probabilistic job symbiosis modeling, which predicts whether jobs will create positive or negative symbiosis when coscheduled without requiring the coschedule to be evaluated. The model, which uses per-thread cycle stacks computed through a previously proposed cycle accounting architecture, is simple enough to be used in system software. Probabilistic job symbiosis modeling provides six key innovations over prior work in symbiotic job scheduling: (i) it does not require a sampling phase, (ii) it readjusts the job coschedule continuously, (iii) it evaluates a large number of possible coschedules at very low overhead, (iv) it is not driven by heuristics, (v) it can optimize a performance target of interest (e.g., system throughput or job turnaround time), and (vi) it preserves system-level priorities/shares. These innovations make symbiotic job scheduling both practical and effective. Our experimental evaluation, which assumes a realistic scenario in which jobs come and go, reports an average 16% (and up to 35%) reduction in job turnaround time compared to the previously proposed SOS (sample, optimize, symbios) approach for a two-thread SMT processor, and an average 19% (and up to 45%) reduction in job turnaround time for a four-thread SMT processor.