Multi-threaded Environment Research Articles

Connecting Things to the IoT by Using Virtual Peripherals on a Dynamically Multithreaded Cortex M3

The Internet of Things communicates with the world by using a wide range of different sensors and actuators. These interfaces are based on a wide range of various protocols, such as I2C, SPI, RS232, 1-wire, and so on. There are two conceptional different solutions to provide these interfaces. One is to use dedicated hardware for it. An example would be to use a peripheral on a system-on-a-chip (SoC). All SoC providers offer the families of SoC solutions with different kind of hardware peripheral combinations. The alternative concept it to run virtual peripherals as a software routine on a CPU, preferable on a multithreaded CPU. C-Slow Retiming (CSR) is a known design transformation to generate multithreaded CPUs. This paper argues, that system hyper pipelining overcomes the limitations of CSR by adding thread stalling, bypassing, and reordering techniques to better cope with the challenges of multithreading. This dynamic multithreaded environment is ideal for running virtual peripheral. The benefits of using system hyper pipelining for virtual peripherals are demonstrated on a Cortex M3-based system.

ASSOCIATION RULE MINING USING BIO INSPIRED BEES SWARM INTELLIGENCE ON CUDA

Association Rule mining (ARM) is well studied and famous optimization problem which finds useful rules from given transactional databases. Many algorithms already proposed in literature which shows their efficiency when dealing with different sizes of datasets. Unfortunately, their efficiency is not enough for handling large scale datasets. Bio inspiredbees swarm intelligence algorithm for association rule mining is more efficient. These kinds of problems need more powerful processors and are time expensive. For such issues solution can be provided by graphics processing units (GPUs). They are massively multithreaded processors. In this case GPUs can be used to increase speed of the computation. Bees swarm intelligence algorithm for association rule mining can be designed using GPUs in multithreaded environment which will efficient for given datasets.

ICE: A memory-efficient BGP route collecting engine

Since their deployment, BGP route collectors have played a fundamental role in investigating and detecting routing accidents and hijack attempts. However, an increasing number of detection techniques designed for real-time environments show that the lack of interactivity of route collectors represents a limitation to their efficacy, together with the small amount of sources from which data is collected. Both issues stem from the current implementation of route collectors, which relies on single-threaded and general-purpose routing suites to establish BGP sessions and collect data. With this implementation any interactive operation impacts on the collection process and the number of sessions that can be established is limited by memory usage, which is not optimized for route collecting purposes. In this paper we present ICE, a multi-threaded and memory-efficient BGP collecting engine which allows route collectors to overcome the above mentioned limitations. The multi-threaded environment allows us to solve the lack of interactiveness, allowing concurrent read/write operations. Memory efficiency has been obtained thanks to the design of a variant of the Liv-Zempel compression algorithms specifically tailored to operate within a BGP real-time collecting environment. The proposed technique exploits the high degree of repetitiveness characterizing BGP data and reduces the ICE memory usage by as much as 30%.

Energy-Aware Paired Sampling-Based Decision Model for Dynamic Mobile-to-Mobile Service Offloading

Power models are a critical element in current research regarding the effect of program-offloading decision making on the energy consumption of mobile devices. Several utilization-based power models have been proposed for measuring the energy consumption of locally running programs. However, the main challenge of utilization-based methods is that the models must be retrained for program units that use hardware components not addressed in the training phase. This paper proposes a paired sampling-based power model to address this critical challenge. The proposed power model estimates the energy consumption of an OSGi service asynchronously invoked in a multithreading environment on the basis of the overall remaining battery energy information at runtime without a connected power meter or energy profile for each specific hardware component of different devices. On the basis of the power model, an offloading decision model is proposed to dynamically determine whether a service invocation should be offloaded to a nearby mobile device over Bluetooth to conserve energy. The proposed approach was experimentally assessed regarding the correctness of decision making, energy gained by offloading service invocations, and weighted absolute percentage error of the estimated energy consumption compared with actual one.

Centroid averaging algorithm for a clustering ensemble

A collective approach to cluster analysis is considered in the paper. An algorithm of centroid averaging is proposed. The algorithm allows constructing the consensus partition of a dataset into clusters, using a set of partitions built with any centroid-based algorithm. We discuss results of applying the proposed algorithm to modeled data and for the segmentation of hyperspectral images with noise channels. Some details of implementation in a multithreaded environment that allows increasing the algorithm performance are given.

Efficient and thread-safe objects for dynamically-typed languages

We are in the multi-core era. Dynamically-typed languages are in widespread use, but their support for multithreading still lags behind. One of the reasons is that the sophisticated techniques they use to efficiently represent their dynamic object models are often unsafe in multithreaded environments. This paper defines safety requirements for dynamic object models in multithreaded environments. Based on these requirements, a language-agnostic and thread-safe object model is designed that maintains the efficiency of sequential approaches. This is achieved by ensuring that field reads do not require synchronization and field updates only need to synchronize on objects shared between threads. Basing our work on JRuby+Truffle, we show that our safe object model has zero overhead on peak performance for thread-local objects and only 3% average overhead on parallel benchmarks where field updates require synchronization. Thus, it can be a foundation for safe and efficient multithreaded VMs for a wide range of dynamic languages.

Abstract Interpretation of Java Bytecode for Immutability Analysis

Even though immutability is a desirable property, especially in a multi-threaded environment, implementing immutable Java classes is surprisingly hard because of a lack of language support. We present a static analysis tool using abstract bytecode interpretation that checks Java classes for compliance with a set of rules that together constitute state-based immutability. Being realized as a Find Bugs plug in, the tool can easily be integrated into most IDEs and hence the software development process. Our evaluation on a large, real world codebase shows that the average run- time effort for a single class is in the range of a few milliseconds, with only a very few statistical spikes.

오픈소스 IDS/IPS Snort와 Suricata의 탐지 성능에 대한 비교 연구

【Recent growth of hacking threats and development in software and technology put Network security under threat, In addition, intrusion, malware and worm virus have been increased due to the existence of variety of sophisticated hacking methods. The goal of this study is to compare Snort Alpha version with Suricata 2.0.11 version whereas previous study focuses on comparison between snort 2. x version under thread environment and Suricata under multi-threading environment. This thesis' experiment environment is set as followed. Intel (R) Core (TM) i5-4690 3. 50GHz (4threads) of CPU, 16GB of RAM, 3TB of Seagate HDD, Ubuntu 14.04 are used. According to the result, Snort Alpha version is superior to Suricata in performance, but Snort Alpha had some glitches when executing pcap files which created core dump errors. Therefore this experiment seeks to analyze which performs better between Snort Alpha version that supports multi packet processing threads and Suricata that supports multi-threading. Through this experiment, one can expect the better performance of beta and formal version of Snort in the future.】

Performance Comparison and Detection Analysis in Snort and Suricata Environment

Recently, crimes are cause in the internet by hacking to target one's and the companies financial. Due to the massive crimes that are caused by digital convergence and ubiquitous IT system, it is clear that the amount of network packet which need to be processed are rising. The digital convergence and ubiquitous IT system caused the IDS (Intrusion Detection System) to process packets more than the past. Snort (version 2.x) is a leading open source IDS which has a long history but since it was built a long time ago, it has several limitations which are not fit for today's requirements. Such as, it's processing unit is in single threading. On the other hand, Suricara was built to cover Snorts these disadvantages. To cover massive amount of packets which are caused by digital convergence and ubiquitous IT system Suricata's have the availability to process packets in multi-threading environment. In this paper we have analyzed and compared Snort and Suricata's processing and detection rate to decide which is better in single threading or multi-threading environment.

GATALSS: A Generic Automated Tool for Analysing the Legacy Software Systems

The software development is primarily more important for the business organization due to its dynamic changes that has to be carried out in a less span of time. Consequently, software reuse will improves the quality of the product, increases the productivity and reduces the costs in an organization. This study presents generic automated tools for analyzing the legacy software systems, which consists of loader, set of parsers and dependency mapper that visualize and transforms different legacy codes. Moreover, we have adopted ANTLR tool to analyze the Legacy Software Systems using multi-threaded environment.

Multiagent Systems Based Modeling and Implementation of Dynamic Energy Management of Smart Microgrid Using MACSimJX.

The objective of this paper is implementation of multiagent system (MAS) for the advanced distributed energy management and demand side management of a solar microgrid. Initially, Java agent development environment (JADE) frame work is used to implement MAS based dynamic energy management of solar microgrid. Due to unstable nature of MATLAB, when dealing with multithreading environment, MAS operating in JADE is linked with the MATLAB using a middle ware called Multiagent Control Using Simulink with Jade Extension (MACSimJX). MACSimJX allows the solar microgrid components designed with MATLAB to be controlled by the corresponding agents of MAS. The microgrid environment variables are captured through sensors and given to agents through MATLAB/Simulink and after the agent operations in JADE, the results are given to the actuators through MATLAB for the implementation of dynamic operation in solar microgrid. MAS operating in JADE maximizes operational efficiency of solar microgrid by decentralized approach and increase in runtime efficiency due to JADE. Autonomous demand side management is implemented for optimizing the power exchange between main grid and microgrid with intermittent nature of solar power, randomness of load, and variation of noncritical load and grid price. These dynamics are considered for every time step and complex environment simulation is designed to emulate the distributed microgrid operations and evaluate the impact of agent operations.

ROOT 6 and beyond: TObject, C++14 and many cores.

Following the release of version 6, ROOT has entered a new area of development. It will leverage the industrial strength compiler library shipping in ROOT 6 and its support of the C++11/14 standard, to significantly simplify and harden ROOT's interfaces and to clarify and substantially improve ROOT's support for multi-threaded environments. This talk will also recap the most important new features and enhancements in ROOT in general, focusing on those allowed by the improved interpreter and better compiler support, including I/O for smart pointers, easier type safe access to the content of TTrees and enhanced multi processor support.

A new concurrency control mechanism for multi-threaded environment using transactional memory

Software transactional memory (STM) is one of the techniques used towards achieving non-blocking process synchronization in multi-threaded computing environment. In spite of its high potential, one of the major limitations of transactional memory (TM) is that in order to ensure data consistency as well as progress condition, TM often forces transactions to abort. This paper proposes a new concurrency control mechanism. It starts with the existing TM implementations for obstruction freedom and eventually builds a new STM methodology. The primary objective is to reduce aborting of transactions in some typical scenarios. A programming model is described for a chain of update transactions that share the same data object among themselves. Using the proposed approach, any new update transaction appended in this chain need not wait for the earlier transactions to finish. The proposed STM allows wait-free, non-blocking implementation of a mix of read and multiple update transactions on the same shared data object with higher throughput.

Hardware implementation based on FPGA of semaphore management in μC/OS-II real-time operating system

Semaphore is a kind of mechanism used in a multithreaded environment to ensure that two or more key code segments are not concurrently invoked. In order to enhance the response capability of real-time operating systems, a hardware design scheme to implement semaphore management based on field programmable gate array is put forward in this paper. We take the μC/OS-II real-time operating system as an example to design hardware logical circuits of semaphore management function module according to its parallel characteristics, and simulation tests under Xilinx ISE software environment are performed. The simulation results show that implementing semaphore management by hardware can obviously improve the execution time of creating/deleting a semaphore, applying for/releasing a semaphore and P/V operations; therefore, the whole reliability of the real-time operating system is greatly improved.

Compiler Optimization for Reducing Leakage Power in Multithread BSP Programs

Multithread programming is widely adopted in novel embedded system applications due to its high performance and flexibility. This article addresses compiler optimization for reducing the power consumption of multithread programs. A traditional compiler employs energy management techniques that analyze component usage in control-flow graphs with a focus on single-thread programs. In this environment the leakage power can be controlled by inserting on and off instructions based on component usage information generated by flow equations. However, these methods cannot be directly extended to a multithread environment due to concurrent execution issues. This article presents a multithread power-gating framework composed of multithread power-gating analysis (MTPGA) and predicated power-gating (PPG) energy management mechanisms for reducing the leakage power when executing multithread programs on simultaneous multithreading (SMT) machines. Our multithread programming model is based on hierarchical bulk-synchronous parallel (BSP) models. Based on a multithread component analysis with dataflow equations, our MTPGA framework estimates the energy usage of multithread programs and inserts PPG operations as power controls for energy management. We performed experiments by incorporating our power optimization framework into SUIF compiler tools and by simulating the energy consumption with a post-estimated SMT simulator based on Wattch toolkits. The experimental results show that the total energy consumption of a system with PPG support and our power optimization method is reduced by an average of 10.09% for BSP programs relative to a system without a power-gating mechanism on leakage contribution set to 30%; and the total energy consumption is reduced by an average of 4.27% on leakage contribution set to 10%. The results demonstrate our mechanisms are effective in reducing the leakage energy of BSP multithread programs.

Parallel Task Management Library for MARTe

The Multithreaded Application Real-Time executor (MARTe) is a real-time framework with increasing popularity and support in the thermonuclear fusion community. It allows modular code to run in a multi-threaded environment leveraging on the current multi-core processor (CPU) technology. One application that relies on the MARTe framework is the Joint European Torus (JET) tokamak WAll Load Limiter System (WALLS). It calculates and monitors the temperature on metal tiles and plasma facing components (PFCs) that can melt or flake if their temperature gets too high when exposed to power loads. One of the main time consuming tasks in WALLS is the calculation of thermal diffusion models in real-time. These models tend to be described by very large state-space models thus making them perfect candidates for parallelisation. MARTe’s traditional approach for task parallelisation is to split the problem into several Real-Time Threads, each responsible for a self-contained sequential execution of an input-to-output chain. This is usually possible, but it might not always be practical for algorithmic or technical reasons. Also, it might not be easily scalable with an increase in the number of available CPU cores. The WorkLibrary introduces a “GPU-like approach” of splitting work among the available cores of modern CPUs that is (i) straightforward to use in an application, (ii) scalable with the availability of cores and all of this (iii) without rewriting or recompiling the source code. The first part of this article explains the motivation behind the library, its architecture and implementation. The second part presents a real application for WALLS, a parallel version of a large state-space model describing the 2D thermal diffusion on a JET tile.

Quatrain: Accelerating Data Aggregation between Multiple Layers

Composition of multiple layers (or components/services) has been a dominant practice in building distributed systems, meanwhile aggregation has become a typical pattern of data flows nowadays. However, the efficiency of data aggregation is usually impaired by multiple layers due to amplified delay. Current solutions based on data/execution flow optimization mostly counteract flexibility, reusability, and isolation of layers abstraction. Otherwise, programmers have to do much error-prone manual programming to optimize communication, and it is complicated in a multithreaded environment. To resolve the dilemma, we propose a new style of inter-process communication that not only optimizes data aggregation but also retains the advantages of layered (or component-based/service-oriented) architecture. Our approach relaxes the traditional definition of procedure and allows a procedure to return multiple times. Specifically, we implement an extended remote procedure calling framework Quatrain to support the new multireturn paradigm. In this paper, we establish the importance of multiple returns, introduce our very simple semantics, and present a new synchronization protocol that frees programmers from multireturn-related thread coordination. Several practical applications are constructed with Quatrain, and the evaluation shows an average of 56% reduction of response time, compared with the traditional calling paradigm, in realistic environments.

Special issue on soft computing techniques in cluster and grid computing systems

The resolution of complex problems requires the use of advanced approximate algorithms and huge computational resources to find accurate solutions in reasonable time. Computing clusters, as well as GPGPUs, grids, and cloud computing infrastructures arise as appropriate innovative computing platforms to implement and execute such algorithms and find accurate solutions to complex problems arising in many application areas. This special issue contains extended versions of the best papers presented in HPCLATAM-2012 and SCCG-2012 conferences, as well as other novel contributions. In total, 27 papers were submitted to the special issue, from which only 10 were finally accepted for publication. These are outstanding contributions proposing novel designs of highly efficient parallel algorithms to solve complex problems, or dealing with salient problems in the fields of grid and cloud computing. In the first paper of this compilation, “Approximating Static List Schedules in Dynamic Multithreaded Applications”, Camargo et al. propose in their contribution the use of list algorithms to optimally schedule algorithms in a multi-thread environment. The difficulty of the approach deals with the fact that a dynamic environment is considered, and no assumptions are assumed to be known about the programs. A novel algorithm is presented to build a directed cyclic graph representing a multithread program from a data flow description, in form of a directed acyclic graph. Several

GMRace: Detecting Data Races in GPU Programs via a Low-Overhead Scheme

In recent years, GPUs have emerged as an extremely cost-effective means for achieving high performance. While languages like CUDA and OpenCL have eased GPU programming for nongraphical applications, they are still explicitly parallel languages. All parallel programmers, particularly the novices, need tools that can help ensuring the correctness of their programs. Like any multithreaded environment, data races on GPUs can severely affect the program reliability. In this paper, we propose GMRace, a new mechanism for detecting races in GPU programs. GMRace combines static analysis with a carefully designed dynamic checker for logging and analyzing information at runtime. Our design utilizes GPUs memory hierarchy to log runtime data accesses efficiently. To improve the performance, GMRace leverages static analysis to reduce the number of statements that need to be instrumented. Additionally, by exploiting the knowledge of thread scheduling and the execution model in the underlying GPUs, GMRace can accurately detect data races with no false positives reported. Our experimental results show that comparing to previous approaches, GMRace is more effective in detecting races in the evaluated cases, and incurs much less runtime and space overhead.

Aproximating static list schedules in dynamic multithreaded applications

List scheduling algorithms are known to be efficient when the application to be executed can be described statically as a Directed Acyclic Graph (DAG) of tasks. Regardless of knowing the entire DAG beforehand, obtaining an optimal schedule in a parallel machine is a NP-hard problem. Moreover, many programming tools propose the use of scheduling techniques based on list strategies. This paper presents an analysis of scheduling algorithms for multithread programs in a dynamic scenario where threads are created and destroyed during execution. We introduce an algorithm to convert DAGs, describing applications as tasks, into Directed Cyclic Graphs (DCGs) describing the same application designed in a multithread programming interface. Our algorithm covers case studies described in previous works, successfully mapping from the abstract level of graphs to the application environment. These mappings preserve the guarantees offered by the abstract model, providing efficient scheduling of dynamic programs that follow the intended multithread model. We conclude the paper presenting some performance results we obtained by list schedulers in dynamic multithreaded environments. We also compare these results with the best scheduling we could obtain with similar static task schedulers.