Multistage Opamp Research Articles

A two‐step sizing method for multistage Op Amps based on behavioral initial sizing followed by Spice‐in‐the‐loop refining

AbstractAnalog integrated circuit sizing is a laborious process that requires many times of iteration with Spice simulations. Even by applying the method, it still requires iterations and test assignment of device values (and biasings) in each iteration until reaching a satisfactory sizing result. When facing a design of multiple‐stage circuits (such as multiple‐stage operational amplifier [Op Amp]), sizing becomes more challenging due to the requirement on pole‐zero placement in order to achieve a better high‐frequency performance. Simulation‐in‐the‐loop method has been the dominating means taken by a great many of existing circuit sizer, but they suffer from intolerable runtime while lacking the possibility of offering insight or design knowledge acquisition. On the other hand, behavioral‐level synthesis methods, although intuitive and fast, suffer from accuracy loss due to the adoption of simplified device models and significantly condensed design equations. However, a proper combination of these two types of methods could lead to a lucrative research territory, yet it demands a methodological development for efficient deployment in practice, namely, implementation easy, less runtime, and guaranteed sizing quality. In this paper, we propose a two‐step method that takes the advantage of behavioral synthesis (in the first step) that is capable of fast and broader coverage of design space then makes correction (in the second step) on sizing refining by Spice simulation. Due to the profiling knowledge acquired on the design space in the first step, it can avoid blindness of the optimization landscape that is faced by many simulation‐centric methods which could easily get trapped in local optima. Conducted experiments over eight three‐stage Op Amps with different compensation configurations, including nested Miller capacitor (NMC), NMC with feedforward path (NMCF), NMC with feedforward path and nulling resistor (NMCFNR), NMC with nulling resistor (NMCNR), double pole‐zero cancellation (DPZC), transconductance with capacitances feedback compensation (TCFC), impedance adapting compensation (IAC), active feedback frequency compensation (AFFC), have validated that the proposed method can successfully generate qualified sizing results, offering an opportunity to compare fairly what merit a specific compensation strategy could possibly have.

Multistage Op Amp design space exploration by gm/ID sampling and symbolic design equations

SummaryMultiple‐stage complementary metal‐oxide‐semiconductor (CMOS) operational amplifiers (Op Amps) have been extensively studied in the literature; often, each new design reports several performance advancements over the existing ones. However, the design space boundaries of those new proposals were rarely explored. Predicting the design space boundary of a new circuit topology is usually challenging due to the dependency on many aspects of technical consideration regarding the process technology, sizing priority adopted in practice, and balancing of performance metrics on power, area, noise immunity, and so on. Knowing the design space boundary could be beneficial to a fair appraisal of new designs. In this paper, we propose a gm/ID‐based method for the design space exploration of multistage Op Amps. By introducing a sampling technique while taking advantage of the device grouping property with gm/ID, it is possible to explore the circuit performance boundary by combining approximate symbolic modeling and gm/ID table lookup. Due to the introduction of a fast performance evaluation method, a large ensemble of circuit sizing samples can be evaluated in parallel, by which an efficient data mining procedure could be incorporated to deduce the circuit samples that can achieve extremal performance at Pareto boundaries. The fidelity of this proposal has been validated via simulation program with integrated circuit emphasis (SPICE) . The sampling method is also compared with a multi‐objective genetic algorithm to show the superiority in capturing Pareto boundaries.

FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmposition

This article presents a method to automatically synthesize the structure and initial sizing of an operational amplifier. It is positioned between approaches with fixed design plans and a small search space of structures and approaches with generic structural production rules and a large search space with technically impractical structures. The presented approach develops a hierarchical composition graph based on functional blocks that spans a search space of thousands of technically meaningful structure variants for single-output, fully differential, and complementary operational amplifiers. The search algorithm is a combined heuristic and enumerative process. The evaluation is based on circuit sizing with a library of behavioral equations of functional blocks. Formalizing the knowledge of functional blocks in op-amps for structural synthesis and sizing inherently reduces the search space and lessens the number of created topologies not fulfilling the specifications. Experimental results for the three op-amp classes are presented. An outlook how this method can be extended to multi-stage op-amps is given.

Sizing of multi-stage Op Amps by combining design equations with the gm/ID method

Analog integrated circuit design has as integral parts both analytical reasoning and numerical validation in the process from topology construction to sizing. Given a circuit topology, different circuit sizing results can be obtained from different processes of sizing inference. Sizing methods by simulation-based numerical searching have been a continuously studied subject. However, almost all approaches in this category require an overwhelming number of circuit simulations to arrive at an optimized sizing result. On the other hand, many published manual sizing methods by using the conventional device equations also require repeated SPICE simulations to correct the equation-based sizing results. This paper proposes a systematic gm/ID-based initial sizing method specifically customized for designing multiple-stage operational amplifiers (Op Amps). A main feature of the proposal is to use circuit-level design equations as constraints on the gm/ID table lookup method to substantially reduce the uncertainty in the sizing calculations. As a result, a significant amount of SPICE based correction work can be reduced to complete an initial sizing. The proposed sizing procedure includes a few regular sizing rules customized to the configuration of multi-stage Op Amps. We validate the proposed sizing method by application to several multi-stage Op Amp examples with a capacitive load or Miller compensation. Simulations have justified that the produced initial sizing results can achieve most of the prespecified design targets.

Improvement of Gain Accuracy and CMRR of Low Power Instrumentation Amplifier Using High Gain Operational Amplifiers

Background: Sensing of biomedical signals is crucial for monitoring of various health conditions. These signals have a very low amplitude (in μV) and a small frequency range (<500 Hz). In the presence of various common-mode interferences, biomedical signals are difficult to detect. Instrumentation amplifiers (INAs) are usually preferred to detect these signals due to their high commonmode rejection ratio (CMRR). Gain accuracy and CMRR are two important parameters associated with any INA. This article, therefore, focuses on the improvement of the gain accuracy and CMRR of a low power INA topology. Objective: The objective of this article is to achieve high gain accuracy and CMRR of low power INA by having high gain operational amplifiers (Op-Amps), which are the building blocks of the INAs. Methods: For the implementation of the Op-Amps and the INAs, the Cadence Virtuoso tool was used. All the designs and implementation were realized in 0.18 μm CMOS technology. Results: Three different Op-Amp topologies namely single-stage differential Op-Amp, folded cascode Op-Amp, and multi-stage Op-Amp were implemented. Using these Op-Amp topologies separately, three Op-Amp-based INAs were realized and compared. The INA designed using the high gain multistage Op-Amp topology of low-frequency gain of 123.89 dB achieves a CMRR of 164.1 dB, with the INA’s gain accuracy as good as 99%, which is the best when compared to the other two INAs realized using the other two Op-Amp topologies implemented. Conclusion: Using very high gain Op-Amps as the building blocks of the INA improves the gain accuracy of the INA and enhances the CMRR of the INA. The three Op-Amp-based INA designed with the multi-stage Op-Amps shows state-of-the-art characteristics as its gain accuracy is 99% and CMRR is as high as 164.1 dB. The power consumed by this INA is 29.25 μW by operating on a power supply of ±0.9V. This makes this INA highly suitable for low power measurement applications.

Analytical distortion calculation method for CMOS amplifier stages

Operational amplifiers (opamps) are often designed in stages. Distortion analysis of multistage opamps is challenging due to multiple non-linearity sources. Therefore, one effective analysis method is to consider a multistage opamp model as a cascade of condensed stages, with each stage modelled by one weakly non-linear element. Then, in order to obtain a satisfactory distortion model, accurate characterisation of the non-linearity of each stage is necessary. In this Letter, the authors propose an analytical calculation method for modelling the weak non-linearity of an amplifier stage consisting of several interconnected transistors. A stage circuit model created by this method can be used to produce analytical harmonic distortion characterisation of closed-loop circuits with peripheral elements. Numerical accuracy of the analytical method has been validated by transistor-level simulation.

Automatic Stage-form Circuit Reduction for Multistage Opamp Design Equation Generation

An automatic stage-form circuit reduction method for multistage operational amplifiers (opamps) is proposed. A tool based on this method can reduce a multistage opamp into a condensed stage-form macromodel, from which design equations can be generated automatically by another existing symbolic program. The proposed model generation method is fully symbolic; namely, it does not make reference to any numerical device values with a circuit, hence it does not require circuit biasing and sizing at an early design stage. The parameters coming with the generated models are dominant-effect approximation of the stage-related characteristics of the original circuits and thus are visually readable for design reasoning. Compensations in the original circuits are extracted automatically and reserved in the macromodel circuits. The user of this tool is only required to input the circuit stage information by identifying several key devices in the original circuits. As design equations can also be automatically generated from stage-form macromodels by a purely symbolic method, the proposed model generation method completes the path from a transistor-level opamp circuit to its characteristic design equations in a completely formal way. Examples are provided to demonstrate the effectiveness of the proposed model generation method, and numerical validation is further carried out to verify that the reduced symbolic models can successfully capture the key circuit behavior in the frequency domain for multistage opamps.

Applying design equations in particle swarm optimization for auto-sizing of multi-stage opamps: an experimental study

This paper presents an experimental study on using analytical design equations in the particle swarm optimization (PSO) for the automatic sizing of multi-stage operational amplifiers (opamps). Differing from the existing research, this work incorporates design equations in the PSO search process in attempt to reduce the search space dimensionality and the number of PSO iterations without sacrificing the quality of search results. Design equations are approximate characterization of the opamp performance metrics in analytical form, which are widely used in manual design process. However, the opamp device sizes cannot be uniquely solved from a set of design equations. Heuristic search can serve as a local optimizer in a reduced-dimensional search space to further refine optimization. Extensive simulation-based experimental PSO search results are presented to demonstrate the effectiveness of the proposed auto-sizing tactic. An alternative genetic algorithm based search method is implemented as well and tested for comparison.

Topological Approach to Symbolic Pole–Zero Extraction Incorporating Design Knowledge

This paper addresses the problem of automatic analytical pole-zero (PZ) extraction for multistage operational amplifiers (opamps) with frequency compensation. Traditional methods mainly rely on numerical reference to derive approximate PZ expressions without incorporating any design knowledge. Such methods suffer from bad interpretability of the auto-generated results. This paper takes a topological approach and attempts to advocate that certain form of design knowledge can be incorporated in the symbolic term selection process for PZ generation. The generation engine selects the dominant terms by a formal inspection on the token patterns that are correlated to gain factors and compensation elements. Since the gain factors and compensation elements of an opamp are pertinent to the topological details of a circuit, the proposed PZ extraction method is closer to design conception than other numerical reference-based methods. Consequently, the generated pole/zero results are better interpretable. Application to a class of multistage opamps with a variety of compensation structures demonstrates that the proposed method is effective and can match human-derived results.

A 6-mW, 70.1-dB SNDR, and 20-MHz BW Continuous-Time Sigma-Delta Modulator Using Low-Noise High-Linearity Feedback DAC

A 4-bit, third-order, continuous-time $\Sigma \Delta$ modulator is presented for use in wireless communications systems. Based on small-signal noise models, analyses for reducing noise in the feedback digital-to-analog converter (DAC) are presented in detail. This enables easy performance/area optimization for the DAC unit elements and the RC noise filter in the DAC bias circuits. To obtain high linearity while simplifying the DAC design, circuit- and layout-level design techniques for minimizing switching time mismatches among and inside the DAC unit elements are presented. As a result, glitch-induced harmonic distortion is greatly reduced, requiring only a simple data-weighted averaging for the multibit DAC. In combination with multipath multistage op amps used to implement active-RC integrators, the presented techniques make it feasible to design a high-performance $\Sigma \Delta$ modulator with low power and small area, which is desired in many wireless communications systems. The experimental prototype, implemented in a 28-nm CMOS technology, achieves a 72.6-dB dynamic range, a 70.7-dB peak SNR, and a 70.1-dB peak signal-to-noise plus distortion ratio for a signal bandwidth of 20 MHz. The total power consumption is 6 mW from a 1- and 1.4-V supply, of which analog and digital circuits dissipate 4.5 and 1.5 mW, respectively. The total active area is 0.058 mm2.

Compensation Method for Multistage Opamps With High Capacitive Load Using Negative Capacitance

It is shown that negative capacitance (NC) circuits can be systematically used to improve the gain–bandwidth product of the operational amplifiers (opamps). The NC circuit moves the nondominant pole of the opamp to higher frequency by decreasing the parasitic capacitance of the critical node. The impedance at the input of the NC circuits is neither purely capacitive nor negative at all frequencies. A design guide is presented by deriving the circuit model for a conventional NC circuit and investigating the extent of the improvement that can be achieved in a circuit by the use of the NC circuit. The model is then used to present the design guide for widebanding the multistage opamps with large capacitive loads. Based on the proposed method, a three-stage opamp with a 15-nF capacitive load was designed and fabricated in a 0.18- $\mu\text{m}$ CMOS process. The measurements confirm that the opamp satisfies the design target of 1.5-MHz bandwidth at the power consumption of 75 $\mu\text{W}$ .