Multi-project Wafer Run Research Articles

AWG-Based Photonic Transmitter With DBR Mirrors and Mach–Zehnder Modulators

In this letter, we demonstrate a novel monolithically integrated photonic multiwavelength transmitter that was realized by integrating an arrayed waveguide grating-based laser with selective distributed Bragg reflector mirrors and Mach-Zehnder modulators. The integrated circuit was designed according to a generic integration model, by utilizing standardized photonic building blocks, and was fabricated on an InP-based platform in a multiproject wafer run. The device delivers above 1 mW of optical power into the fiber with a side mode suppression ratio better than 40 dB. The linewidth of the generated signals is 275 kHz. We achieved error free 50-km transmission at the modulation data rate of 10 Gb/s per channel, for a received power of -26.5 dBm.

InP-Based Photonic Multiwavelength Transmitter With DBR Laser Array

We demonstrate an InP-based photonic multiwavelength transmitter realized by integrating an array of distributed Bragg reflector lasers with modulators in Mach-Zehnder configuration. An arrayed waveguide grating is used to multiplex the generated signals into a common optical output. The device is designed according to a generic integration concept, using standardized building blocks, and is fabricated in a multiproject wafer run. The device delivers up to 4 dBm of optical power into the fiber with a modulation data rate of 12.5 Gbps per transmission channel. The obtained performance makes it very promising for application in the next generation optical access networks as a key source in the central office part of the telecommunication systems.

Data readout system utilizing photonic integrated circuit

We describe a novel optical solution for data readout systems. The core of the system is an Indium-Phosphide photonic integrated circuit performing as a front-end readout unit. It functions as an optical serializer in which the serialization of the input signal is provided by means of on-chip optical delay lines. The circuit employs electro-optic phase shifters to build amplitude modulators, power splitters for signal distribution, semiconductor optical amplifiers for signal amplification as well as on-chip reflectors. We present the concept of the system, the design and first characterization results of the devices that were fabricated in a multi-project wafer run.

95 GHz millimeter wave signal generation using an arrayed waveguide grating dual wavelength semiconductor laser

We report the generation of a 95 GHz carrier frequency by optical heterodyning of two wavelengths from adjacent channels from an arrayed waveguide grating-based multiwavelength laser. The extended cavity structure of the device provides low phase noise and narrow optical linewidth, further enhanced by the intracavity filter effect of the arrayed waveguide grating. We demonstrate that the generated RF beat note, at 95 GHz, has a -3 dB linewidth of 250 kHz. To the best of our knowledge, this is the narrowest RF linewidth generated from a free-running dual-wavelength semiconductor laser. The device is realized as a photonic integrated circuit using active-passive integration technology, and fabricated on a multiproject wafer run, constituting a novel approach for a compact, low-cost dual-wavelength heterodyne source.

A 256 channel 8-Bit current digitizer ASIC for the Belle-II PXD

The international DEPFET collaboration is developing a silicon pixel vertex detector (PXD), based on monolithic arrays of DEPFET transistors, for the future physics experiment Belle-II at the SuperKEKB particle accelerator in Japan. The matrix elements are read out in a 'rolling shutter mode', i.e. rows are selected consecutively and all columns are read out in each cycle of < 100 ns.One of the major parts in the front-end electronics chain is the DEPFET Current Digitizer ASIC (DCDB). It is now in a close-to-final state. The chip provides 256 channels of analog-to-digital converters with a resolution of six to eight bits. Each converter features an individual dynamic offset correction circuit as well as programmable gain and bandwidth. Several operation modes using single sampling or double correlated sampling are possible.A large synthesized digital block is used for decoding and derandomization of the conversion results. The data is put out on eight 8-bit links, operating at a speed of 400 MHz. Additionally, a JTAG compatible interface is implemented for configuration and debugging purpose.Significant effort was made to reduce the power consumption of the DCDB, since both, voltage drop on the internal power buses and heat sources in the Belle-II experiment are a concern.The chip was realized on a 3.2mm × 5mm die using the UMC 180nm CMOS technology in a multi-project wafer run, provided by EuroPractice. An extra redistribution metal layer with bump bond pads is used, allowing for flipping the chip onto the final all-silicon DEPFET sensor module.Several tests have been performed in order to prove the chip's operation and its quality in terms of noise. The results are presented.

Chip placement in a reticle for multiple-project wafer fabrication

Chip placement in a reticle is crucial to the cost of a multiproject wafer run. In this article we develop several chip placement methods based on the volume-driven compatibility optimization (VOCO) concept, which maximizes dicing compatibility among chips with large-volume requirements while minimizing reticle dimensions. Our mixed-integer linear programming models with VOCO are too complex to render good solutions for large test cases. Our B*-tree with VOCO and HQ with VOCO use 16%∼ 29% fewer wafers and 8%∼ 19% less reticle area than the hierarchical quadrisection (HQ) method proposed by Kahng et al. [2005]