Multiprogramming System Research Articles

The Cause and Treatment Strategy on Thrashing

Producing in the multiprogramming systems of the demanding paging style ,thrashing is an extreme status coming from doing page replacement. Based on some research results, the cause of thrashing is discussed with describing the feature of it. A policy of "preventing first" is presented to hold on to refrain from the thrashing ,which sets forth the concrete method of preventing and ending the thrashing. Some relating conclusions are also fit for page replacements of the computer designing in other fields.

CPU SCHEDULING SIMULATION

CPU scheduling is the basis of multiprogrammed operating system. By switching the CPU among processes, the operating system can make the computer more productive. The objective of multiprogramming is to have some process running at all times, in order to maximize CPU utilization. This paper presents a simulator that uses graphical representation to convey the concepts of various scheduling algorithms for a single CPU. It allows the user to test and increase his understanding of the concepts studied by making his own scheduling decisions, through the very easy graphical user interface of the simulator. It graphically depicts each process in terms of what the process is currently doing against time. Using this representation it becomes much easier to understand what is going on inside the system and why different set of processes are candidate for allocation of the CPU at different time.In this paper, we introduce the basic scheduling concepts and present several different CPU – scheduling algorithms in visual way.

Flexible Decoupled Transactional Memory Support

A high-concurrency transactional memory (TM) implementation needs to track concurrent accesses, buffer speculative updates, and manage conflicts. We present a system, FlexTM (FLEXible Transactional Memory), that coordinates four decoupled hardware mechanisms: read and write signatures, which summarize per-thread access sets; per-thread conflict summary tables (CSTs), which identify the threads with which conflicts have occurred; Programmable Data Isolation, which maintains speculative updates in the local cache and employs a thread-private buffer (in virtual memory) in the rare event of overflow; and Alert-On-Update, which selectively notifies threads about coherence events. All mechanisms are software-accessible, to enable virtualization and to support transactions of arbitrary length. FlexTM allows software to determine when to manage conflicts (either eagerly or lazily), and to employ a variety of conflict management and commit protocols. We describe an STM-inspired protocol thatuses CSTs to manage conflicts in a distributed manner (no global arbitration) and allows parallel commits. In experiments with a prototype on Simics/GEMS, FlexTM exhibits 5x speedup over high-quality software TM, with no loss in policy flexibility. Its distributed commit protocol is also more efficient than a central hardware manager. Our results highlight the importance of flexibility in determining when to manage conflicts: lazy maximizes concurrency and helps to ensure forward progress while eager provides better overall utilization in a multi-programmed system.

Obituary: Per Brinch Hansen (1938–2007)

The Editors and Publishers of Software—Practice and Experience regret to note the passing of Per Brinch Hansen on 31 July 2007. Professor Brinch Hansen was a member of the journal's editorial board from 1979 until earlier this year. Per Brinch Hansen was a leading figure in the development of operating systems and multiprocessing concepts. His many accomplishments during a very productive lifetime included the RC 4000 multiprogramming system, the monitor concept, the Concurrent Pascal language, the Solo operating system, and the Edison programming language. Several of his most influential papers were published in this journal. His career took him from the Regnecentralen, Copenhagen, to Carnegie Mellon University, California Institute of Technology, University of California, and the University of Copenhagen. His final position, which he held up to the time of his death, was at Syracuse University in New York state. Along the way, he authored nine academic books published in the conventional manner, plus his autobiography published on the internet at http://brinch-hansen.net.

Cost-effective use of breast biopsy techniques in a veterans health care system

Background Breast health has become an increasingly important issue among the veteran population. Options for the evaluation of a breast mass or a suspicious mammographic finding include open surgical biopsy at the Veterans Affairs (VA) hospital or percutaneous image-guided biopsy at an affiliated academic institution. We examined the costs and trends in the use of surgical versus percutaneous image-guided biopsy procedures in this diagnostic algorithm. Methods A retrospective review was performed of 62 patients who presented to the VA General Surgery Clinic with a breast mass or abnormal mammogram from 2003 to 2005. The Massachusetts Utilization Multiprogramming System and the Decision Support System software packages were used to track costs of procedures, by Current Procedure Terminology code and date of service, performed at the affiliated academic institution and at the VA hospital. These data were analyzed and described using the R statistical computing environment. Results Forty-six patients were evaluated using open biopsy techniques in the VA operating room, including 8 incisional biopsies, 21 excisional biopsies, and 17 needle-localization excisional biopsies. Sixteen patients were evaluated using minimally invasive biopsies at the affiliated academic institution, including 3 ultrasound-guided cyst aspirations, 6 ultrasound-guided core biopsies/vacuum-assisted core biopsies, 10 stereotactic breast biopsies, and 1 fine-needle aspiration. The average cost to evaluate a breast mass or abnormal mammographic finding in the operating room was $4,368.00 (SD, $2,586.00), with a median cost of $3,479.00. The average cost to evaluate a breast mass or mammographic abnormality using percutaneous image-guided procedures was $1,267.00 (SD, $536.00), with a median of $1,239.00. From 2003 to 2005, the proportion of percutaneous biopsies increased from 13% to 48%, whereas the proportion of open biopsies decreased from 88% to 52%. Conclusions Over a recent 3-year period, we observed a 3.8-fold increase in the use of percutaneous image-guided techniques for the evaluation of breast lesions in the VA Tennessee Valley Healthcare System. Diagnosis by percutaneous techniques allows planning for a definitive surgery if a lesion is malignant or possible avoidance of a surgical intervention if the lesion is benign. Our data show that the costs associated with open biopsy techniques exceed those associated with percutaneous biopsies. For VA hospitals with available resources, the option of image-guided percutaneous biopsy techniques is a cost-effective alternative to open surgical biopsy.

Teaching principles of shared resource management with the MOSES2 microcomputer operating system environment

Every modern multiprogramming computer operating system must effectively manage and protect resources that are shared among the different user processes that run simultaneously on the system. Resou...

Adaptive parallel I/O scheduling algorithm for multiprogrammed systems

As the rate at which disk drives read and write data is improving at a much slower pace than the speed of processors, I/O has risen to become the bottleneck in high-performance computing for many applications. A possible approach to address this problem is to schedule parallel I/O operations explicitly. To this end, we propose two new I/O scheduling algorithms and evaluate the relative performance of the proposed policies against two baseline policies. Simulation results show that the proposed policies outperform the baseline policies.

Performance-driven processor allocation

In current multiprogrammed multiprocessor systems, to take into account the performance of parallel applications is critical to decide an efficient processor allocation. In this paper, we present the performance-driven processor allocation policy (PDPA). PDPA is a new scheduling policy that implements a processor allocation policy and a multiprogramming-level policy, in a coordinated way, based on the measured application performance. With regard to the processor allocation, PDPA is a dynamic policy that allocates to applications the maximum number of processors to reach a given target efficiency. With regard to the multiprogramming level, PDPA allows the execution of a new application when free processors are available and the allocation of all the running applications is stable, or if some applications show bad performance. Results demonstrate that PDPA automatically adjusts the processor allocation of parallel applications to reach the specified target efficiency, and that it adjusts the multiprogramming level to the workload characteristics. PDPA is able to adjust the processor allocation and the multiprogramming level without human intervention, which is a desirable property for self-configurable systems, resulting in a better individual application response time.

An efficient high quality random number generator for multi-programmed systems

This document presents an efficient, high quality random number generator for multi-programmed environments, in particular for UNIX/Linux and Windows systems. The algorithm uses a system's notion of the time, given by a high-precision real-time count

An efficient high quality random number generator for multi-programmed systems

This document presents an efficient, high quality random number generator for multi-programmed environments, in particular for UNIX/Linux and Windows systems. The algorithm uses a system's notion o...

Token-ordered LRU: an effective page replacement policy and its implementation in Linux systems

Most computer systems use a global page replacement policy based on the LRU principle to approximately select a Least Recently Used page for a replacement in the entire user memory space. During execution interactions, a memory page can be marked as LRU even when its program is conducting page faults. We define the LRU pages under such a condition as false LRU pages because these LRU pages are not produced by program memory reference delays, which is inconsistent with the LRU principle. False LRU pages can significantly increase page faults, even cause system thrashing. This poses a more serious risk in a large parallel systems with distributed memories because of the existence of coordination among processes running on individual node. In the case, the process thrashing in a single node or a small number of nodes could severely affect other nodes running coordinating processes, even crash the whole system. In this paper, we focus on how to improve the page replacement algorithm running on one node. After a careful study on characterizing the memory usage and the thrashing behaviors in the multi-programming system using LRU replacement. we propose an LRU replacement alternative, called token-ordered LRU, to eliminate or reduce the unnecessary page faults by effectively ordering and scheduling memory space allocations. Compared with traditional thrashing protection mechanisms such as load control, our policy allows more processes to keep running to support synchronous distributed process computing. We have implemented the token-ordered LRU algorithm in a Linux kernel to show its effectiveness.

Dynamic tracking of page miss ratio curve for memory management

Memory can be efficiently utilized if the dynamic memory demands of applications can be determined and analyzed at run-time. The page miss ratio curve(MRC), i.e. page miss rate vs. memory size curve, is a good performance-directed metric to serve this purpose. However, dynamically tracking MRC at run time is challenging in systems with virtual memory because not every memory reference passes through the operating system (OS).This paper proposes two methods to dynamically track MRC of applications at run time. The first method is using a hardware MRC monitor that can track MRC at fine time granularity. Our simulation results show that this monitor has negligible performance and energy overheads. The second method is an OS-only implementation that can track MRC at coarse time granularity. Our implementation results on Linux show that it adds only 7--10% overhead.We have also used the dynamic MRC to guide both memory allocation for multiprogramming systems and memory energy management. Our real system experiments on Linux with applications including Apache Web Server show that the MRC-directed memory allocation can speed up the applications' execution/response time by up to a factor of 5.86 and reduce the number of page faults by up to 63.1%. Our execution-driven simulation results with SPEC2000 benchmarks show that the MRC-directed memory energy management can improve the Energy * Delay metric by 27--58% over previously proposed static and dynamic schemes.

Dynamic tracking of page miss ratio curve for memory management

Memory can be efficiently utilized if the dynamic memory demands of applications can be determined and analyzed at run-time. The page miss ratio curve(MRC), i.e. page miss rate vs. memory size curve, is a good performance-directed metric to serve this purpose. However, dynamically tracking MRC at run time is challenging in systems with virtual memory because not every memory reference passes through the operating system (OS).This paper proposes two methods to dynamically track MRC of applications at run time. The first method is using a hardware MRC monitor that can track MRC at fine time granularity. Our simulation results show that this monitor has negligible performance and energy overheads. The second method is an OS-only implementation that can track MRC at coarse time granularity. Our implementation results on Linux show that it adds only 7--10% overhead.We have also used the dynamic MRC to guide both memory allocation for multiprogramming systems and memory energy management. Our real system experiments on Linux with applications including Apache Web Server show that the MRC-directed memory allocation can speed up the applications' execution/response time by up to a factor of 5.86 and reduce the number of page faults by up to 63.1%. Our execution-driven simulation results with SPEC2000 benchmarks show that the MRC-directed memory energy management can improve the Energy * Delay metric by 27--58% over previously proposed static and dynamic schemes.

Dynamic tracking of page miss ratio curve for memory management

Memory can be efficiently utilized if the dynamic memory demands of applications can be determined and analyzed at run-time. The page miss ratio curve(MRC), i.e. page miss rate vs. memory size curve, is a good performance-directed metric to serve this purpose. However, dynamically tracking MRC at run time is challenging in systems with virtual memory because not every memory reference passes through the operating system (OS).This paper proposes two methods to dynamically track MRC of applications at run time. The first method is using a hardware MRC monitor that can track MRC at fine time granularity. Our simulation results show that this monitor has negligible performance and energy overheads. The second method is an OS-only implementation that can track MRC at coarse time granularity. Our implementation results on Linux show that it adds only 7--10% overhead.We have also used the dynamic MRC to guide both memory allocation for multiprogramming systems and memory energy management. Our real system experiments on Linux with applications including Apache Web Server show that the MRC-directed memory allocation can speed up the applications' execution/response time by up to a factor of 5.86 and reduce the number of page faults by up to 63.1%. Our execution-driven simulation results with SPEC2000 benchmarks show that the MRC-directed memory energy management can improve the Energy * Delay metric by 27--58% over previously proposed static and dynamic schemes.

Behaviour of passage time for a queueing network model withfeedback: a simulation study

The study of the queueing system presented in this note was motivated by its possible application to a multiprogramming computer system. The paper considers a closed network with two service centres with feedback. The steady‐state behaviour of the passage time, the random times for a job to traverse a portion of the network, is examined through simulation. The model can be applied to a twin‐processor multiprogramming computer system.

Dynamically adapting to system load and program behavior in multiprogrammed multiprocessor systems

AbstractParallel execution of application programs on a multiprocessor system may lead to performance degradation if the workload of a parallel region is not large enough to amortize the overheads associated with the parallel execution. Furthermore, if too many processes are running on the system in a multiprogrammed environment, the performance of the parallel application may degrade due to resource contention. This work proposes a comprehensive dynamic processor allocation scheme that takes both program behavior and system load into consideration when dynamically allocating processors. This mechanism was implemented on the Solaris operating system to dynamically control the execution of parallel C and Java application programs. Performance results show the effectiveness of this scheme in dynamically adapting to the current execution environment and program behavior, and that it outperforms a conventional time‐shared system. Copyright © 2002 John Wiley & Sons, Ltd.

Implementing a dynamic processor allocation policy for multiprogrammed parallel applications in the SolarisTM

AbstractParallel applications typically do not perform well in a multiprogrammed environment that uses time‐sharing to allocate processor resources to the applications' parallel threads. Co‐scheduling related parallel threads, or statically partitioning the system, often can reduce the applications' execution times, but at the expense of reducing the overall system utilization. To address this problem, there has been increasing interest in dynamically allocating processors to applications based on their resource demands and the dynamically varying system load. The Loop‐Level Process Control (LLPC) policy (Yue K, Lilja D. Efficient execution of parallel applications in multiprogrammed multiprocessor systems. 10th International Parallel Processing Symposium, 1996; 448–456) dynamically adjusts the number of threads an application is allowed to execute based on the application's available parallelism and the overall system load. This study demonstrates the feasibility of incorporating the LLPC strategy into an existing commercial operating system and parallelizing compiler and provides further evidence of the performance improvement that is possible using this dynamic allocation strategy. In this implementation, applications are automatically parallelized and enhanced with the appropriate LLPC hooks so that each application interacts with the modified version of the Solaris operating system. The parallelism of the applications are then dynamically adjusted automatically when they are executed in a multiprogrammed environment so that all applications obtain a fair share of the total processing resources. Copyright © 2001 John Wiley & Sons, Ltd.

A scheduling policy for preserving cache locality in a multiprogrammed system

Abstract In a multiprogrammed system, when the operating system switches contexts, in addition to the cost for handling the processes being swapped out and in, the cache performance of processors also can be affected. If frequent context switching replaces the data loaded into cache memory before they are completely reused, the programs suffer from cache misses due to the damage in cache locality. In particular, for the programs with good cache locality, such as blocked programs, a scheduling mechanism of keeping cache locality against context switching is essential to achieve good processor utilization. To solve this requirement, we propose a preemption-safe policy to exploit the cache locality of blocked programs in a multiprogrammed system. The proposed policy delays context switching until a block is fully reused, but also compensates for the monopolized processor time on processor scheduling mechanisms. Our simulation results show that in a situation where blocked programs are run on multiprogrammed shared-memory multiprocessors, the proposed policy improves the performance of these programs due to a decrease in cache misses. In such situations, it also has a beneficial impact on the overall system performance due to the enhanced processor utilization.

Swap compression: resurrecting old ideas

The performance of memory-intensive applications tends to be poor due to the high overhead added by the swapping mechanism. The same problem may be found in highly-loaded multi-programming systems where all running applications have to use the swap space in order to be able to execute at the same time. In this paper, we present a solution to these problems. The idea consists of compressing the swapped pages and keeping them in a swap cache whenever possible. The idea of a compressed swap cache was proposed a few years ago, but it did not achieve the expected results due to hardware limitations. As processors are much faster and the performance gap between processors and disk is also much bigger, we believe that now it is the right time to revisit this idea. In this paper, we present a new implementation of the compressed cache, plus some enhancements that significantly improve the performance of the swapping mechanism. Copyright © 2000 John Wiley & Sons, Ltd.

Swap compression: resurrecting old ideas

The performance of memory-intensive applications tends to be poor due to the high overhead added by the swapping mechanism. The same problem may be found in highly-loaded multi-programming systems where all running applications have to use the swap space in order to be able to execute at the same time. In this paper, we present a solution to these problems. The idea consists of compressing the swapped pages and keeping them in a swap cache whenever possible. The idea of a compressed swap cache was proposed a few years ago, but it did not achieve the expected results due to hardware limitations. As processors are much faster and the performance gap between processors and disk is also much bigger, we believe that now it is the right time to revisit this idea. In this paper, we present a new implementation of the compressed cache, plus some enhancements that significantly improve the performance of the swapping mechanism. Copyright © 2000 John Wiley & Sons, Ltd.