Multiprocessor System-on-chip Research Articles

FPGA Prototyping and Design Evaluation of a NoC-Based MPSoC

Chip communication architectures become an important element that is critical to control when designing a complex MultiProcessor System-on-Chip (MPSoC). This led to the emergence of new interconnection architectures, like Network-on-Chip (NoC). NoCs have been proven to be a promising solution to the concerns of MPSoCs in terms of data parallelism. Field-Programmable Gate Arrays (FPGA) has some perceived challenges. Overcoming those challenges with the right prototyping solutions is easy and cost-effective leading to much faster time-to-market. In this paper, we present an FPGA based on rapid prototyping in hardware/software co-design and design evaluation of a mixed HW/SW MPSoC using a NoC. A case study of two-dimensional mesh NoC-based MPSoC architecture is presented with a validation environment. The synthesis and implementation results of the NoC-based MPSoC on a Virtex 5 ML 507 enable a reasonable frequency (151.5 MHz) and a resource usage rate equals to 58% (6,586 out of 11,200 slices used).

Massively Parallel ECoG Signal Processing using MPSoC for Real-time Brain–Computer Interface

Bio-medical signal contains large quantities of data and it should be processed in a short period of time face. The development of modern computer based processing system provides extreme support for bio-medical signal analysis. It is a challenging work to process all the data recorded from an electrode array with high channel counts and bandwidth, such as electroencephalographic (EEG) and electrocorticographic (ECoG) grids. Therefore, a novel parallel processing method was developed for real-time neural signal processing of a brain–computer interface (BCI). The Multiprocessor system-on-chip (MPSoC) system was used to offload processing with the support of multi-core technology, which is capable of running many operations in parallel. The proposed design supports reconfigurable embedded computing techniques which can be portable, economical and cost saving system. The BCI system traces many channels of data. It may be processed and translated into a control signal, such as the movement of a cursor towards the indicated direction. This signal processing chain has three steps which are matrix–matrix multiplication technique, power spectral density calculation on every channel and classification of appropriate features for control. In this study, the BCI signal processing chain is implemented on the proposed embedded computing based SoC system, and compared with the current BCI system in terms of speed and accuracy. Significant performance gains were obtained in this study. The current BCI system processed 1000 channels of 250 ms in 1486 ms with 68% accuracy, while the proposed method took only 48 ms, an improvement of nearly 31 times.

Towards Protected MPSoC Communication for Information Protection against a Malicious NoC

Multiprocessor System-on-Chip (MPSoC) design is based on the integration of several third-party Intellectual Property (IP) cores. Some of those IPs may include Trojans, extra hardware that can be triggered during operation time in order to perform an attack. Network-on-Chip (NoC), the communication IP of MPSoCs, can include Trojans that spy, modify and constrain the sensitive communication inside the chip. Although previous works address the malicious NoC threat, finding secure and efficient solutions is still a challenge. In this work, we propose a novel and secure network interface which implements a tunnel-based protocol that enables the secure exchange of sensitive data even in the presence of a malicious NoC. We test our technique with synthetic traffic as well as in several real application scenarios, and show that it is a secure and efficient solution.

Performance Estimation of HEVC/h.265 Decoder in a Co-Design Flow with SADF-FSM Graphs

Multiprocessor System on Chip (MPSoC) technology presents an interesting solution to reduce the computational time of complex applications such as multimedia applications. Implementing the new High Efficiency Video Coding (HEVC/h.265) codec on the MPSoC architecture becomes an interesting research point that can reduce its algorithmic complexity and resolve the real time constraints. The implementation consists of a set of steps that compose the Co-design flow of an embedded system design process. One of the first anf key steps of a Co-design flow is the modeling phase which allows designers to make best architectural choices in order to meet user requirements and platform constraints. Multimedia applications such as HEVC decoder are complex applications that demand increasing degrees of agility and flexibility. These applications are usually modeling by dataflow techniques. Several extensions with several schedules techniques of dataflow model of computation have been proposed to support dynamic behavior changes while preserving static analyzability. In this paper, the HEVC/h.265 video decoder is modeled with SADF based FSM in order to solve problems of placing and scheduling this application on an embedded architecture. In the modeling step, a high-level performance analysis is performed to find an optimal balance between the decoding efficiency and the implementation cost, thereby reducing the complexity of the system. The case study in this case works with the HEVC/h.265 decoder that runs on the Xilinx Zedboard platform, which offers a real environment of experimentation.

Processors Allocation for MPSoCs With Single ISA Heterogeneous Multi-Core Architecture

Single-instruction set architecture (ISA) heterogeneous multi-processor architecture is promising for developing multi-processor system-on-chips (MPSoCs). In this architecture, all processors execute the same instruction set, yet with various performance and power behavior, since processors may have various micro-architectures. Therefore, systems with this architecture have the advantages of easy to develop new functions as the homogeneous architecture, and easy to customize the resource allocation to achieve high energy efficiency as the heterogeneous architecture. However, for an MPSoC utilizing the target architecture, a key design issue is how to select the set of processors so that the target system can achieve good performance while the cost of the chip is constrained to the expected value. To solve this, in this paper, we propose a processor allocation method for MPSoCs with single-ISA heterogeneous multi-core architecture. The goal of the proposed method is to automatically synthesize the allocation of cores for the given workload so that the performance is optimized while the resource constraint is met. To the best of our knowledge, this is the first work that tackles the processor allocation problem for MPSoCs with the target architecture. To bring out the best performance of a hardware configuration, the proposed algorithm also synthesizes the software design of task mapping for a selected hardware configuration. The experimental results show that, compared with the homogeneous architecture with the least cost and lowest performance cores only, even if the number of core is set to the maximum parallelism degree of the target workload, the proposed method achieves up to 8.25% of performance improvement among all the cases we evaluated while the area constraint is met. Compared with the architecture with all high performance but large cores, when the number of cores is also set to the same as the maximum parallelism degree of the target workload, the proposed method has at most 11.5% of performance degradation, while the area cost is reduced by 60.7%.

Software framework for runtime application monitoring of fail-safe multi-processor ADAS SoCs

In advanced driver assistance systems (ADAS), it is very critical to ensure a system malfunction does not cause harm to humans (also referred to as functional safety). Malfunctions could occur due to incorrect software (SW) execution. Many techniques exist to catch systematic SW faults during software and application development. However, without run-time monitoring of key parameters, it is impossible to guarantee a fail-safe system. In this paper, we describe a software framework to monitor application statistics in heterogeneous multiprocessor SoCs targeted for fail-safe ADAS systems. With < 0.5% CPU load overhead per monitor, the proposed framework was found to accurately report statistics for a front camera analytics application.

Software framework for runtime application monitoring of fail-safe multi-processor ADAS SoCs

Software framework for runtime application monitoring of fail-safe multi-processor ADAS SoCs

Pipelined-Scheduling of Multiple Embedded Applications on a Multi-Processor-SoC

Due to clock and power constraints, it is hard to extract more power out of single core architectures. Thus, multi-core systems are now the architecture of choice to provide the needed computing power. In embedded system, multi-processor system-on-a-chip (MPSoC) is widely used to provide the needed power to effectively run complex embedded applications. However, to effectively utilize an MPSoC system, tools to generate optimized schedules is highly needed. In this paper, we design an integrated approach to task scheduling and memory partitioning of multiple applications utilizing the MPSoC system simultaneously. This is in contrast to the traditional decoupled approach that looks at task scheduling and memory partitioning as two separate problems. Our framework is also based on pipelined scheduling to increase the throughput of the system. Results on different benchmarks show the effectiveness of our techniques.

Exploiting performance, dynamic power and energy scaling in full‐system simulators

SummaryEnergy consumption constraints have become a critical issue in Multiprocessor Systems on Chip (MPSoC) designs. Whereas processor performance comes with a high power cost, there is an increasing interest in exploring the trade‐off between power and performance, taking into account the target application domain. Dynamic Voltage and Frequency Scaling (DVFS) techniques adaptively scale frequency or voltage level of CPU allowing it to reach just enough performance to process the system workload while meeting throughput constraints, and thereby, reducing the energy consumption. To explore this wide design space for energy efficiency and performance, hardware and software components, a system‐level simulation infrastructure must provide features to evaluate power savings mechanisms in early stages of the design. This paper presents an extension work of a framework for MPSoCs designs to support DVFS in MPSoCs simulators and evaluates three DVFS mechanisms. Our experiments show that applying DVFS in the system can save power and energy consumption, with negligible loss of performance. Copyright © 2016 John Wiley &amp; Sons, Ltd.

Mapping multiple applications onto 3D NoC-based MPSoCs supporting wireless links

Three-dimensional integrated circuits (3D ICs) are suitable alternatives to traditional two-dimensional (2D) ICs by leveraging its advantage of better performance and packaging; therefore, they have been highly considered by researchers. On the other hand, emerging network-on-chip (NoC) based many-core chips provides great potential for running multiple applications simultaneously. However, using this approach leads to the increase of the interference between applications, resulting in lowering the performance of each application. Hence, mapping tasks belonging to various applications onto the nodes of an architecture is a very important issue. In this study, based on partitioning concept, a novel methodology for mapping of multiple applications at run-time onto an irregular wireless 3D NoC-based multiprocessor system-on-chip (MPSoC) platform in which more than one task can be supported by each processing element (PE) was presented. In the second algorithm (enhanced irregular-partitioning best neighbor), according to the number of applications running simultaneously, the partitioning of network will be dynamically changed to minimize the communication overhead and congestion on the NoC that leads to more efficient task mapping. The simulation results reveal that the second proposed algorithm (enhanced IPBN) in comparison with NPBN (non-partitioning best neighbor) algorithm and our first proposed algorithm (basic IPBN) enhances the performance by decreasing the total execution time, average hop count, average channel load and energy consumption.

Simulating Reconfigurable Multiprocessor Systems-on-Chip with MPSoCSim

Upcoming reconfigurable Multiprocessor Systems-on-Chip (MPSoCs) present new challenges for the design and early estimation of technology requirements due to their runtime adaptive hardware architecture. The usage of simulators offers capabilities to overcome these issues. In this article, MPSoCSim, a SystemC simulator for Network-on-Chip (NoC) based MPSoCs is extended to support the simulation of reconfigurable MPSoCs. Processors, such as ARM and MicroBlaze, and peripheral models used within the virtual platform are provided by Imperas/OVP and attached to the NoC. Moreover, traffic generators are available to analyze the system. The virtual platform currently supports mesh topology with wormhole switching and several routing algorithms such as XY-, a minimal West-First algorithm, and an adaptive West-First algorithm. Amongst the impact of routing algorithms regarding performance, reconfiguration processes can be examined using the presented simulator. A mechanism for dynamic partial reconfiguration is implemented that is oriented towards the reconfiguration scheme on real FPGA platforms. It includes the simulation of the undefined behavior of the hardware region during reconfiguration and allows the adjustment of parameters. During runtime, dynamic partial reconfiguration interfaces are used to connect the Network-on-Chip infrastructure with reconfigurable regions. The configuration access ports can be modeled by the controller for the dynamic partial reconfiguration in form of an application programming interface. An additional SystemC component enables the readout of simulation time from within the application. For evaluation of the simulator timing and power consumption of the simulated hardware are estimated and compared with a real hardware implementation on a Xilinx Zynq FPGA. The comparison shows that the simulator improves the development of reconfigurable MPSoCs by early estimation of system requirements. The power estimations show a maximum deviation of 9mW at 1.9W total power consumption.

Providing fault tolerance through invasive computing

Abstract As a consequence of technology scaling, today's complex multi-processor systems have become more and more susceptible to errors. In order to satisfy reliability requirements, such systems require methods to detect and tolerate errors. This entails two major challenges: (a) providing a comprehensive approach that ensures fault-tolerant execution of parallel applications across different types of resources, and (b) optimizing resource usage in the face of dynamic fault probabilities or with varying fault tolerance needs of different applications. In this paper, we present a holistic and adaptive approach to provide fault tolerance on Multi-Processor System-on-a-Chip (MPSoC) on demand of an application or environmental needs based on invasive computing. We show how invasive computing may provide adaptive fault tolerance on a heterogeneous MPSoC including hardware accelerators and communication infrastructure such as a Network-on-Chip (NoC). In addition, we present (a) compile-time transformations to automatically adopt well-known redundancy schemes such as Dual Modular Redundancy (DMR) and Triple Modular Redundancy (TMR) for fault-tolerant loop execution on a class of massively parallel arrays of processors called as Tightly Coupled Processor Arrays (). Based on timing characteristics derived from our compilation flow, we further develop (b) a reliability analysis guiding the selection of a suitable degree of fault tolerance. Finally, we present (c) a methodology to detect and adaptively mitigate faults in invasive NoCs.

A Lightweight Framework for the Dynamic Creation and Configuration of Virtual Platforms in SystemC

Virtual prototypes leverage SystemC/TLM for simulating programmable platforms comprising hundreds of modules. Their efficient creation and configuration is vital for acceptable turnaround times, for example, during performance exploration or software development. Therefore, our lightweight framework provides a factory that creates designs from abstract descriptions of module instances, properties, and connections. Modules mark properties as creation or runtime parameters. The resulting generic design descriptions are usable by non-experts and enable front-ends. The infrastructure is a small C++ library with only 1,350 lines of code that can be combined with existing SystemC/TLM models and simulation kernels. An industrial case study of a complex multiprocessor SoC shows a distinct productivity gain.

Hardware/Software Partitioning for Heterogenous MPSoC Considering Communication Overhead

Hardware/software partitioning (HSP) is an important step in the co-design of hardware/software. This paper addresses the problem of HSP with communication (HSPC) on heterogeneous multiprocessor system-on-chip (MPSoC). The classic HSP is modeled as an optimization problem with an objective of minimizing the finishing time in system under the hardware area constraints. First, we put forward an optimal method, integer linear programming (ILP) algorithm, for solving the problem for small inputs. Then, we propose two other algorithms using dynamic programming (DP) method, i.e., Optimal Tree Partitioning (OTP) method for tree-structured graphs and Tree Cover Partitioning (TCP) algorithm for general graphs in polynomial time. The overall performance of the proposed algorithms is evaluated through comparisons with that of a genetic algorithm (GA) and a greedy algorithm which are commonly used to solve HSP problem. We have conducted experimental performance evaluation on various benchmarks with different combinations of computation to communication ratios and hardware area constraints. The experimental results show that OTP algorithm can generate optimal solutions with much faster speed than ILP, and TCP algorithm can obtain near-optimum with higher quality than those produced by GA and greedy algorithm.

Application Mapping and Scheduling for Network-on-Chip-Based Multiprocessor System-on-Chip With Fine-Grain Communication Optimization

Network-on-chip (NoC) is promising for the communication paradigm of the next-generation multiprocessor system-on-chip (MPSoC). As communication has become an integral part of on-chip computing, and even the performance bottleneck, researchers are paying much attention to its implementation and optimization. Traditional techniques that model communication inaccurately will lead to unexpected runtime performance, which is on average 90.8% worse than the predicted results based on observation, and are not suitable for the deep optimization of communication-intensive scenarios. In this paper, techniques are presented for the NoC-based MPSoCs that integrate optimization on interprocessor communications with the objective of minimizing the schedule length. A fine-grained integer-linear programming (ILP) model is proposed to properly address the communication latency with a network contention, which generates runtime scheduling with trivial performance difference from the predictions. We further propose a heuristic algorithm, unified priority-based scheduling (UPS), to effectively solve the contention problem in polynomial time by assigning priorities to messages. Evaluation results show that the solutions obtained by the ILP model outperform the state-of-the-art techniques by 31.1%, and UPS improves application performance by 34.7% and 44.4% compared with acquainted first-in-first-out (FIFO)-based and random-based methods. In addition, UPS achieves averagely 8.3% approximated results with the optimal solutions generated by ILP. A case study on H.264 high-definition television (HDTV) decoder and the digital signal processor (DSP) filter benchmarks achieves significant improvement on the performance and the results prediction accuracy, as well as the prominent reduction in the number of network contention and energy consumption.

A New Static Data Flow Clustering Algorithm for Task Scheduling of Irregular Mesh in NoCs Based on Complex Networks

The majority of recent embedded systems are based on MPSoCs (Multi-Processors System on Chip) architectures. The topologies and the interconnections inside multi processors almost adopt NoCs (Networks on Chip) whose topology and task scheduling algorithm have a direct impact on its performances. In this paper, by using static data flow, a task scheduling algorithm which would automatically assign the application tasks onto different processors is proposed based on complex network. The goal of our algorithm is to replace the static data flow subnetwork by a single dynamic data flow actor such that the global performance in terms of latency and throughput is optimized. Through complex network, it greatly enhances the power of our algorithm in terms of avoiding deadlock, saving energy and providing for integration with more general models of computation. Experimental results show up to 60% performance improvement for real-world examples.

Cloud-based Design and Virtual Prototyping Environment for Embedded Systems

The design and test of Multi-Processor System-on-Chips (MPSoCs) and development of distributed applications and/or operating systems executed on those hardware platforms is one of the biggest challenges in today’s system design. This applies in particular when short time-to-market constraints impose serious limitations on the exploration of the design space. The use of virtual platforms can help in decreasing the development and test cycles. In this paper, we present a cloud-based environment supporting the user in designing heterogeneous MPSoCs and developing distributed applications. Therefore, the design environment generates virtual platforms automatically allowing fast prototyping cycles especially in the software development process, and exports the design to a hardware flow synthesizing compatible FPGA designs. The extension of the peripheral models with debug information supports the developer during test and debug cycles and avoids the need of adding special debug codes in the application. This improves the readability, portability and maintainability of produced software. Additionally, this paper presents the benefits of using cloud-based design environments in engineers’ trainings and educations. Therefore, the framework supports testing the system including complex software stacks with prerecorded data or testbenches.

FPGA Implementation of Torus NOC Architecture

Network on Chip architectures (NoC) are considered the next generations interconnect systems for multiprocessor systemson-chip. Selection of the network architecture and mapping of IP nodes onto the NoC topology are two important research topics. Most of the researchers implement the noc architectures either using virtual channel routers or using simulators, but in this paper we implement well known interconnect system specifically 3x3 torus noc architecture using store and forward technique based router architecture in VHDL.

Fast and accurate MPSoC virtual platform simulation with parallel out-of-order execution approach

Virtual platform simulation is one of the most popular simulation techniques for multi-processor system-on-chips (MPSoCs). However, the complexity of modern MPSoCs leads to the unacceptable simulation speed on the virtual platform. To speed up the simulation, we propose a parallel out-of-order execution approach which efficiently applies the computation power of the multi-core system. The proposed approach includes a distributed memory exclusivity technique and a dynamic time-alignment mechanism (DTAM). Using the distributed memory exclusivity technique, multiple processor cores can be executed concurrently and multiple hardware components can be simulated in the out-of-order execution. The DTAM not only increases the simulation accuracy but also detects the parallel execution of the hardware simulation processes. With the benefits of the proposed approach, the experimental results show that the speedup is up to 266X compared to the conventional scheduling approach in SystemC.

Cycle-Accurate Network on Chip Simulation with Noxim

The on-chip communication in current Chip-MultiProcessors (CMP) and MultiProcessor-SoC (MPSoC) is mainly based on the Network-on-Chip (NoC) design paradigm. Unfortunately, it is foreseen that conventional NoC architectures cannot sustain the performance, power, and reliability requirements demanded by the next generation of manycore architectures. Recently, emerging on-chip communication technologies, like wireless Networks-on-Chip (WiNoCs), have been proposed as candidate solutions for addressing the scalability limitations of conventional multi-hop NoC architectures. In a WiNoC, a subset of network nodes are equipped with a wireless interface which allows them long-range communication in a single hop. Assessing the performance and power figures of NoC and WiNoC architectures requires the availability of simulation tools that are often limited on modeling specific network configurations. This article presents Noxim, an open, configurable, extendible, cycle-accurate NoC simulator developed in SystemC, which allows to analyze the performance and power figures of both conventional wired NoC and emerging WiNoC architectures.