Multiprocessor System-on-chip Research Articles

Efficient Architectures for Multigigabit CCSDS LDPC Encoders

Quasi-cyclic low-density parity-check (QC-LDPC) codes have been adopted by the Consultative Committee for Space Data Systems (CCSDS) as the recommended standard for onboard channel coding in Near-Earth and Deep-Space communications. Encoder architectures proposed so far are not efficient for high-throughput hardware implementations targeting the specific CCSDS codes. In this article, we introduce a novel architecture for the multiplication of a dense quasi-cyclic (QC) matrix with a bit vector, which is the fundamental operation of QC-LDPC encoding. The architecture leverages the inherent parallelism of the QC structure by concurrently processing multiple bits, according to an optimized scheduling. Based on this architecture, we propose efficient encoders for CCSDS codes, according to all the applicable low-density parity-check (LDPC) code encoding methods. Moreover, in the special case of the code for Near-Earth communications, we also introduce a preprocessing algorithm to efficiently handle the challenges arising from the generator's matrix circulant size (511 bits). The proposed architectures have been implemented in various field-programmable gate array (FPGA) technologies and validated in Zynq UltraScale+ multiprocessor system-on-chip (MPSoC), achieving a significant speedup compared with previous approaches, while at the same time keeping resource utilization low.

Enforcing Predictability of Many-Cores With DCFNoC

The ever need for higher performance forces industry to include technology based on multi-processors system on chip (MPSoCs) in their safety-critical embedded systems. MPSoCs include a network-on-chip (NoC) to interconnect the cores between them and with memory and the rest of shared resources. Unfortunately, the inclusion of NoCs compromises guaranteeing time predictability as network-level conflicts may occur. To overcome this problem, in this article we propose DCFNoC, a new time-predictable NoC design paradigm where conflicts within the network are eliminated by design. This new paradigm builds on top of the Channel Dependency Graph (CDG) in order to deterministically avoid network conflicts. The network guarantees predictability to applications and is able to naturally inject messages using a TDM period equal to the optimal theoretical bound without the need of using a computationally demanding offline process. DCFNoC is integrated in a tile-based many-core system and adapted to its memory hierarchy. Our results show that DCFNoC guarantees time predictability avoiding network interference among multiple running applications. DCFNoC always guarantees performance and also improves wormhole performance in a $4\times 4$ 4 × 4 setting by a factor of $3.7\times$ 3 . 7 × when interference traffic is injected. For a $8\times 8$ 8 × 8 network differences are even larger. In addition, DCFNoC obtains a total area saving of 10.79 percent over a standard wormhole implementation.

DRHEFT: Deadline-Constrained Reliability-Aware HEFT Algorithm for Real-Time Heterogeneous MPSoC Systems

Heterogeneous multiprocessor system-on-chips (MPSoCs) are suitable platforms for real-time embedded applications that require powerful parallel processing capability as well as low power consumption. For such applications, soft-error reliability (SER) due to transient faults and lifetime reliability (LTR) due to permanent faults are both key concerns. There have been several efforts in the literature oriented toward related reliability problems. However, most existing techniques only concentrate on improving one of the two reliability metrics, which are not suitable for embedded systems deployed in critical applications in need of a long lifetime as well as a reliable execution. This article develops a novel heterogeneous earliest-finish-time (HEFT)-based algorithm to maximize SER and LTR simultaneously under the real-time constraint for dependent tasks executing on heterogeneous MPSoC systems. More specifically, a new deadline-constrained reliability-aware HEFT algorithm, namely DRHEFT, is proposed, which seeks for the best SER–LTR tradeoff solutions through using fuzzy dominance to evaluate the relative fitness values of candidate solutions. The extensive experiments on real-life benchmarks as well as synthetic applications demonstrate that DRHEFT is capable of achieving better SER–LTR tradeoff solutions with higher hypervolume and less computation cost when compared with the state-of-the-art approaches.

Latency Minimization using Mesochronous Scheduling in MPSoC Operation

High speed computing is the upcoming challenge for next generation applications. To cope with high speed operations, new processing architectures are evolving. Multi processor design is one optimal design approach for such need. In the design development of multi processor unit, Multi-Processor System-on-Chip (MPSoC) has an outcome in the domain of VLSI design. MPSoC are designed to process multiple instructions and data handling simultaneously. The parallel processing feature make this unit faster and optimal design for upcoming applications. However, MPSoC operations have a latency issue in clock allocation and resource utilization, which effects the processing efficiency and introduces delay and resource overhead in MPSoC interface. This paper outlines a Mesochronous operation in MPSoC design for minimizing latency in clock allocation and resource allocation, hence improving the speed of operation.

Hardware Trojan Mitigation in Pipelined MPSoCs

Multiprocessor System-on-Chip (MPSoC) has become necessary due to the the billions of transistors available to the designer, the need for fast design turnaround times, and the power wall. Thus, present embedded systems are designed with MPSoCs, and one possible way MPSoCs can be realized is through Pipelined MPSoC (PMPSoC) architectures, which are used in applications from video surveillance to cryptosystems. Hardware Trojans (HTs) on PMPSoCs are a significant concern due to the damage caused by their stealth. An adversary could use HTs to extract secret information (data leakage) to modify functionality/data (functional modification) or make PMPSoCs deny service. In this article, we present PMPGuard, a mechanism that (1) detects the presence of hardware Trojans in Third Party Intellectual Property (3PIP) cores of PMPSoCs by continuous monitoring and testing and (2) recovers the system by switching the infected processor core with another one. We designed, implemented, and tested the system on a commercial cycle accurate multiprocessor simulation environment. Compared to the state-of-the-art system-level techniques that use Triple Modular Redundancy (TMR) and therefore incur at least 3× area and power overheads, our proposed system incurs about 2× area and 1.5× power overheads without any adverse impact on throughput.

Exploiting Multi-Level Parallelism for Run-Time Adaptive Inverse Kinematics on Heterogeneous MPSoCs

This paper presents a run-time solver for the inverse kinematics of a robotic arm implemented on a heterogeneous Multi-Processor System-on-Chip (MPSoC). The solver has been formulated as an optimization problem, in which two levels of algorithmic parallelism are proposed: i) the Nelder-Mead derivative-free method used as the optimization engine is modified to allow the evaluation of the cost function in multiple vertices simultaneously, ii) the trajectory is divided into non-overlapping segments, in which all the points are solved concurrently. Algorithmic parallelism is supported by a variable number of parallel instances of a custom hardware accelerator, which speeds up the computation of the forward kinematics equations of the robot required during the resolution of the inverse kinematics. This adaptable scheme provides run-time scalability in terms of trajectory accuracy, logic resources, dependability, and execution time. New design methodologies are used to unify the modeling of the software and hardware partitions of the controller while transparently providing adaptability. They are based on the dataflow Model of Computation (MoC), supported by the PREESM prototyping tool. This tool has been extended to support the use of dynamically reconfigurable hardware accelerators implemented using the ARTICo3 framework. The proposal has been validated with a python-based robotic arm simulator. Experimental results show how the proposed parallelism, combined with hardware acceleration, enables the run-time resolution of the trajectory with adaptable performance using a Xilinx Zynq UltraScale+ MPSoC device.

Real-Time Hardware-in-the-Loop Emulation of High-Speed Rail Power System With SiC-Based Energy Conversion

Real-time device-level hardware-in-the-loop (HIL) emulation of a complete high-speed rail system is challenging due to its complex modeling and high computing demand. With higher energy-efficient and switching frequency semiconductor material being found and adopted in the power electronic electrified traction application, there is a need to develop such new material based real-time device-level power electronic models in the modern and future traction system to estimate and verify the device switching transients, energy efficiency, and power quality improvement capability. This paper proposes a real-time SiC IGBT model based on the Wiener-Hammerstein configuration. A complete Beijing-Shanghai AC traction application is utilized as the study case, implemented on the hybrid multiprocessor system-on-chip (MPSoC) and field-programmable gate array (FPGA) platform, to verify both the system-level and device-level performance of the proposed model with comparisons to commercial software PSCAD/EMTDC and SaberRD. The dedicated hardware implementation enabled model execution at $10~ns$ for device-level transients and 10 μs for system-level transients.

Run-Time Reconfigurable MPSoC-Based On-Board Processor for Vision-Based Space Navigation

This paper describes a reconfigurable architecture for an on-board processor to be used in space exploration critical systems. It relies on, a dynamically reconfigurable multi-accelerator hardware architecture that provides transparent reconfiguration and scalable performance, dependability, and power consumption, at run-time. The architecture is integrated under an RTEMS operating system, which manages reconfiguration and fault mitigation in a fully-compatible way with space requirements. In this work, the proposed processor is used to implement a vision-based navigation system, providing fully autonomous adaptation to different phases of a space mission timeline or events that the spacecraft may encounter during its lifespan. Results show that reconfigurability enables the practical usage of Commercial Off-The-Shelf (COTS) Multiprocessor Systems-on-Chips (MPSoCs) in real scenarios.

Implementation of SAR Echo Simulation Algorithm on Heterogeneous Embedded Computing Platform

The Synthetic Aperture Radar (SAR) echo simulation is to obtain the SAR original echo signal by performing reverse operation on the pre-set SAR image. The traditional platforms used to implement the simulation algorithms like central processing unit (CPU) + graphic processing unit (GPU) and digital signal processor (DSP) + field programmable gate array (FPGA) have disadvantages such as high power consumption or complicated programming. In order to make up for these shortcomings, the implementation structure of the SAR echo simulation algorithm was improved to be applicable on the heterogeneous embedded platform with the basic SAR simulation algorithms digitized and decomposed. Base on the improved structure, a mobile GPU based heterogeneous computing platform with one multiprocessor system-on-chip (MPSoC) and multiple GPUs was designed to implement SAR echo simulation algorithm. The platform can simultaneously utilize the real-time nature of register transfer level (RTL) design and the ease of programming on GPU. It can achieve relatively faster computing power at lower power consumption and has the characteristics of miniaturization and mobility.

A new architecture for online error detection and isolation in network on chip

The Network-on-Chip (NoC) has become a promising communication infrastructure for Multiprocessors-System-on-Chip (MPSoC). Reliability is a main concern in NoC and performance is degraded when NoC is susceptible to faults. A fault can be determined as a cause of deviation from the desired operation of the system (error). To deal with these reliability challenges, this work propose OFDIM (Online Fault Detection and Isolation Mechanism),a novel combined methodology to tolerate multiple permanent and transient faults. The new router architecture uses two modules to assure highly reliable and low-cost fault-tolerant strategy. In contrast to existing works, our architecture presents less area, more fault tolerance, and high reliability. The reliability comparison using Silicon Protection Factor (SPF), shows 22-time improvement and that additional circuitry incurs an area overhead of 27%, which is better than state-of-the-art reliable router architectures. Also, the results show that the throughput decreases only by 5.19% and minor increase in average latency 2.40% while providing high reliability.

Resource Management for Improving Soft-Error and Lifetime Reliability of Real-Time MPSoCs

Multiprocessor system-on-chip (MPSoC) has been widely used in many real-time embedded systems where both soft-error reliability (SER) and lifetime reliability (LTR) are key concerns. Many existing works have investigated them, but they focus either on handling one of the two reliability concerns or on improving one type of reliability under the constraint of the other. These techniques are thus not applicable to maximize SER and LTR simultaneously, which is highly desired in some real-world applications. In this paper, we study the joint optimization of SER and LTR for real-time MPSoCs. We propose a novel static task scheduling algorithm to simultaneously maximize SER and LTR for real-time homogeneous MPSoC systems under the constraints of deadline, energy budget, and task precedence. Specifically, we develop a new solution representation scheme and two evolutionary operators that are closely integrated with two popular multiobjective evolutionary optimization frameworks, namely NSGAII and SPEA2. Extensive experimental results on standard benchmarks and synthetic applications show the efficacy of our scheme. More specifically, our scheme can achieve significantly better solutions (i.e., LTR-SER tradeoff fronts) with remarkably higher hypervolume and can be dozens or even hundreds of times faster than the state-of-the-art algorithms. The results also demonstrate that our scheme can be applied to heterogeneous MPSoC systems and is effective in improving reliability for heterogeneous MPSoC systems.

Literary Study of Memory Architectures for Multiprocessor System on Chip (MPSoC)

Literary Study of Memory Architectures for Multiprocessor System on Chip (MPSoC)

Energy-Aware Schedules Under Chip Reliability Constraint for Multi-Processor Systems-on-a-Chip

Even though multi-core systems are effective architectures to overcome the limitation of single-core systems, techniques to improve reliability, throughput and power consumption are highly needed. With the increasing complexity of multi-processor systems-on-a-chip (MPSoCs) to handle the ever increasing complexity of embedded computing applications, the reliability of such systems is now a big concern in the industry. Complex MPSoCs typically have multiple execution modes with different throughput and reliability performances. These complex embedded systems are also expected to perform under minimum power and energy consumptions. In this paper, we present efficient techniques for low-energy and thermal-aware schedules that meet the deadlines under chip reliability constraints. The presented techniques under different objective functions are implemented and executed on multiple embedded applications under multiple underlying system architectures to show the performance and efficiency of the techniques.

Energy-efficient Static Task Scheduling on VFI-based NoC-HMPSoCs for Intelligent Edge Devices in Cyber-physical Systems

The interlinked processing units in modern Cyber-Physical Systems (CPS) creates a large network of connected computing embedded systems. Network-on-Chip (NoC)-based Multiprocessor System-on-Chip (MPSoC) architecture is becoming a de facto computing platform for real-time applications due to its higher performance and Quality-of-Service (QoS). The number of processors has increased significantly on the multiprocessor systems in CPS; therefore, Voltage Frequency Island (VFI) has been recently adopted for effective energy management mechanism in the large-scale multiprocessor chip designs. In this article, we investigated energy-efficient and contention-aware static scheduling for tasks with precedence and deadline constraints on intelligent edge devices deploying heterogeneous VFI-based NoC-MPSoCs (VFI-NoC-HMPSoC) with DVFS-enabled processors. Unlike the existing population-based optimization algorithms, we proposed a novel population-based algorithm called ARSH-FATI that can dynamically switch between explorative and exploitative search modes at run-time. Our static scheduler ARHS-FATI collectively performs task mapping, scheduling, and voltage scaling. Consequently, its performance is superior to the existing state-of-the-art approach proposed for homogeneous VFI-based NoC-MPSoCs. We also developed a communication contention-aware Earliest Edge Consistent Deadline First (EECDF) scheduling algorithm and gradient descent--inspired voltage scaling algorithm called Energy Gradient Decent (EGD). We introduced a notion of Energy Gradient (EG) that guides EGD in its search for island voltage settings and minimize the total energy consumption. We conducted the experiments on eight real benchmarks adopted from Embedded Systems Synthesis Benchmarks (E3S). Our static scheduling approach ARSH-FATI outperformed state-of-the-art technique and achieved an average energy-efficiency of ∼24% and ∼30% over CA-TMES-Search and CA-TMES-Quick, respectively.

Augmented Cross-Entropy-Based Joint Temperature Optimization of Real-Time 3-D MPSoC Systems

3-D multiprocessor system-on-chip (MPSoC) systems can offer higher integration density, lower interaction cost, better bandwidth, and greater performance. However, vertically stacked silicon layers and limited heat dissipation paths result in high peak temperature and large temperature variation, which incur reliability reduction, lifetime decay, and performance degradation. In this article, we propose an offline augmented cross-entropy (CE)-based task scheduling strategy to jointly optimize peak temperature and temperature variation under the constraint of timeliness. Specifically, based on the conventional CE method, a heuristic iterative sampling method is designed to explore task-to-core assignment for balanced heat distribution between the top-layer and the bottom-layer cores. Subsequently, thermal characteristics of 3-D MPSoC systems are used to judiciously swap tasks between the two layers to improve the conventional CE-based task assignment and accelerate the iterative process. The peak temperature of individual cores is further reduced via sequencing, splitting, and slacking task execution. The experimental results demonstrate that compared to the existing state-of-the-art methods, the proposed scheme can reduce peak temperature by up to 8.02 °C and temperature variation by up to 24.78% without violating the timeliness of tasks.

Mitigating single event upset method for Zynq MPSoC

Single event upset (SEU) have direct influence on the reliability of Zynq Multi-Processor System-on-Chip (MPSoC). To mitigate SEU, the method based on the structural features of the two ARM cores in Zynq is proposed. Dual-core mutual detection and rollback recovery are utilized to detect and repair the errors caused by SEU. Hsiao code is also integrated to enhance the SEU-resistance of on-chip memory. Experimental results show that the proposed method can correct error of ARMs and on-chip memory error.

P‐EdgeCoolingMode: an agent‐based performance aware thermal management unit for DVFS enabled heterogeneous MPSoCs

Thermal cycling, as well as spatial and thermal gradient, affects the lifetime reliability and performance of heterogeneous Multi-Processor Systems-on-Chips (MPSoCs). Conventional temperature management techniques are not intelligent enough to cater for performance, energy efficiency as well as the operating temperature of the system. In this study, the authors propose a light-weight novel thermal management mechanism (P-EdgeCoolingMode) in the form of intelligent software agent, which monitors and regulates the operating temperature of the CPU cores to improve the reliability of the system while catering for performance requirements. P-EdgeCoolingMode is capable of pro-actively monitoring performance and based on the user's demand the agent takes necessary action, making the proposed methodology highly suitable for implementation on existing as well as conceptual Edge devices utilising heterogeneous MPSoCs with dynamic voltage and frequency scaling (DVFS) capabilities. They validated the authors’ methodology on the Odroid-XU4 MPSoC and Huawei P20 Lite (HiSilicon Kirin 659 MPSoC). P-EdgeCoolingMode has been successful in reducing the operating temperature while improving performance and reducing power consumption for chosen test cases than the state-of-the-art. For applications with demanding performance requirement P-EdgeCoolingMode has been found to improve the power consumption by 30.62% at the most in comparison to existing state-of-the-art power management methodologies.

DAMHSE: Programming heterogeneous MPSoCs with hardware acceleration using dataflow-based design space exploration and automated rapid prototyping

Heterogeneous Multiprocessor Systems-on-a-Chip (MPSoCs) with programmable hardware acceleration are currently gaining market share in the embedded device domain. Largest MPSoCs combine several software processing cores with programmable logic. In these systems, reaching the optimal implementation performance is difficult because many manual and time-consuming steps are required to build, from the application specification, a prototype with measurable performances. In this paper, a method is developed that, based on state-of-the-art tools and High-Level Synthesis, deploys within less than an hour a whole hardware-software rapid prototype from a unique dataflow-based application representation: DAMHSE (DAtaflow Method for Hardware/Software Exploration). A human-driven Design Space Exploration (DSE) is conducted in order to find the most performing architectural solution, and compilable/synthesizable code is generated. The method has been tested on an image processing system with software and hardware parallelism. Results show that the obtained absolute performance (pixel/cycles) reaches state-of-the-art, and that DAMHSE leads to a heterogeneous system where performance increases significantly when the application is granted with more hardware resources.One of the greatest challenges in creating such a design automation method resides in the application behavior that may change over time and affect application concurrency and system performance. In order to overcome this problem, the design-time DAtaflow Method for Hardware/Software Exploration (DAMHSE) method is complemented with a runtime application management system that dynamically dispatches jobs (tasks) among the available processing elements (CPUs and/or hardware accelerators). Experimental results show that the performance penalty due to runtime application mapping and scheduling is limited and that the computational performance of the adaptive system remains high. Apart from the vendor-specific HLS, the tools and the frameworks used by the proposed method are open source and tutorials are available to reproduce the results.

Crosstalk Noise Aware System For WDM-Based Optical Network on Chip

Network on chip (NoC) is presented as a promising solution to face off the growing up of the data exchange in the multiprocessor system-on-chip (MPSoC). However, the traditional NoC faces two main problems: the bandwidth and the energy consumption. To face off these problems, a new technology in MPSoC, namely, optical network-on-chip (ONoC) has been introduced which it uses the optical communication to guaranty a high performance in communication between cores. In addition, wavelength division multiplexing (WDM) is exploited in ONoC to reach a high rate of bandwidth. Nevertheless, the transparency nature of the ONoC components induce crosstalk noise to the optical signals, which it has a direct effect to the signal-to-noise ratio (SNR) then decrease the performance of the ONoC. In this paper, we proposed a new system to control these impairments in the network in order to detect and monitor crosstalk noise in WDM-based ONoC. Furthermore, the crosstalk monitoring system is a distributed hardware system designed and test with the different optical components according the various network topology used in ONoC. The register-transfer level (RTL) hardware design and implementation of this system can result in high reliability, scalability and efficiency with running time less than 20 ms.

SPIDER-based Out-of-Order Execution Scheme for Ht-MPSOC

In this work, the influence of the dynamic task scheduling process is examined. Out-of-order (OoO) implementation processes exhibit remarkable guarantee for task-level parallelism in multiprocessor system-on-chip (MPSOC) designs. The superior performance can be attained with the help of a precise mapping of tasks onto the right processors. Hence, to obtain this performance, a SPIDER-based task parallelism is presented in this work. The software related dynamic operations are illustrated on a heterogeneous MPSOC (Ht-MPSOC). SPIDER abides by a cooperative population-based search, which demonstrates upon the social activities of SPIDER grouping. SPIDER system merges local search approaches with global search approaches. This implementation decreases the issue of task management. The performance of the proposed design is compared with the existing work for power, area and speed analysis.