Multiprocessor SoC Architectures Research Articles

Run-Time Remapping Algorithm of Dataflow Actors on NoC-Based Heterogeneous MPSoCs

Multiprocessor system-on-chip (MPSoC) platforms have been emerging as the main solution to cope with processor frequency ceiling and power density issues while still improving performances. Then, network-on-chip (NoC) has been adopted to provide the increasing number of processors with the required communication bandwidth as well as with the necessary flexibility. Video processing and streaming applications are adopting dynamic dataflow model of computation as the need for high performance parallel computing is growing. Dataflow applications executed on modern MPSoC-based architectures are becoming increasingly dynamic and more data-dependent. Different tasks execute concurrently with significant modifications in their workloads and resource demanding over time depending on the input data. Hence, adopting any static or offline dynamic scheduling for mapping tasks will not cope with the computation variations. This article introduces an original run-time mapping algorithm based on the Move Based (MB) method targeting a dedicated heterogeneous NoC-based MPSoC architecture to achieve workload balancing and optimized communication traffic. The performance of the proposed algorithm is verified by conducting cycle-accurate SystemC simulations of the adopted NoC implementing a real MPEG4-SP decoder. The obtained results reveal the effectiveness of our proposed algorithm. For various real-life videos, the proposed algorithm systematically succeeded to enhance significantly the performance.

Hardware Trojan Mitigation in Pipelined MPSoCs

Multiprocessor System-on-Chip (MPSoC) has become necessary due to the the billions of transistors available to the designer, the need for fast design turnaround times, and the power wall. Thus, present embedded systems are designed with MPSoCs, and one possible way MPSoCs can be realized is through Pipelined MPSoC (PMPSoC) architectures, which are used in applications from video surveillance to cryptosystems. Hardware Trojans (HTs) on PMPSoCs are a significant concern due to the damage caused by their stealth. An adversary could use HTs to extract secret information (data leakage) to modify functionality/data (functional modification) or make PMPSoCs deny service. In this article, we present PMPGuard, a mechanism that (1) detects the presence of hardware Trojans in Third Party Intellectual Property (3PIP) cores of PMPSoCs by continuous monitoring and testing and (2) recovers the system by switching the infected processor core with another one. We designed, implemented, and tested the system on a commercial cycle accurate multiprocessor simulation environment. Compared to the state-of-the-art system-level techniques that use Triple Modular Redundancy (TMR) and therefore incur at least 3× area and power overheads, our proposed system incurs about 2× area and 1.5× power overheads without any adverse impact on throughput.

DoS Attack Detection and Path Collision Localization in NoC-Based MPSoC Architectures

Denial of Service (DoS) attacks are an increasing threat for Multiprocessor System-on-Chip (MPSoC) architectures. By exploiting the shared resources on the chip, an attacker is able to prevent completion or degrade the performance of a task. This is extremely dangerous for MPSoCs used in critical applications. The Network-on-Chip (NoC), as a central MPSoC infrastructure, is exposed to this attack. In order to maintain communication availability, NoCs should be enhanced with an effective and precise attack detection mechanism that allows the triggering of effective attack mitigation mechanisms. Previous research works demonstrate DoS attacks on NoCs and propose detection methods being implemented in NoC routers. These countermeasures typically led to a significantly increased router complexity and to a high degradation of the MPSoC’s performance. To this end, we present two contributions. First, we provide an analysis of information that helps to narrow down the location of the attacker in the MPSoC, achieving up to a 69% search space reduction for locating the attacker. Second, we propose a low cost mechanism for detecting the location and direction of the interference, by enhancing the communication packet structure and placing communication degradation monitors in the NoC routers. Our experiments show that our NoC router architecture detects single-source DoS attacks and determines, with high precision, the location and direction of the collision, while incurring a low area and power overhead.

Sustainability-Oriented Evaluation and Optimization for MPSoC Task Allocation and Scheduling under Thermal and Energy Variations

Aiming at high performance, more and more Cyber-Physical Systems (CPSs) adopt Multiprocessor System-on-Chips (MPSoCs) as computation units. However, due to increasing integration of transistors on a die, the power densities together with performance variations of MPSoC chips have been increasing dramatically. Consequently, the MPSoC-based CPSs might become unsustainable and unreliable. Although various Task Allocation and Scheduling (TAS) heuristics have been proposed to minimize the hotspot time (i.e., duration of thermal emergency) and energy consumption of MPSoC designs, few of them can guarantee the highest performance yield under process variations without violating energy, thermal and timing constraints. To address these challenges, this paper proposes a novel energy- and thermal-aware TAS evaluation and optimization framework. Based on statistical model checking techniques, our approach enables accurate modeling and reasoning of the performance yield of real-time MPSoC designs under joint energy and thermal constraints. To enable system-level design space exploration, we propose a regression analysis-based method that can drastically reduce the overall exploration efforts. Experimental results show that our fully-automated approach can not only allow accurate sustainability-oriented reasoning of TAS solutions under specified thermal and energy constraints, but also enable the quick search of optimal TAS solutions on different MPSoC architectures with the highest performance yield.

Runtime Techniques to Mitigate Soft Errors in Network-on-Chip (NoC) Architectures

As aggressive scaling continues to push multiprocessor system-on-chips (MPSoCs) to new limits, complex hardware structures combined with stringent area and power constraints will continue to diminish reliability. Waning reliability in integrated circuits will increase the susceptibility of transient and permanent faults. There is an urgent demand for adaptive error correction coding (ECC) schemes in network-on-chips to provide fault tolerance and improve overall resiliency of MPSoC architectures. The goal of adaptive ECC schemes should be to maximize power savings when faults are infrequent and increase application speedup by boosting fault coverage when faults are frequent. In this paper, we propose runtime adaptive scrubbing (RAS), a novel multilayered error correction and detection scheme with three modes of operation enabled by an area-efficient configurable encoder for encoding packets on the switch-to-switch (s2s) layer, thus preventing faults from accumulating up the network stack and onto the end-to-end layer. As fault rates fluctuate we propose a dynamic methodology for improving fault localization and intelligently adapt fault coverage on demand to sustain graceful network degradation. RAS successfully improves network resiliency, fault localization, and fault coverage as compared to traditional static s2s schemes. Simulation results demonstrate that static RAS improves network speedup by 10% for Splash-2/PARSEC benchmarks on a $8 \times 8$ mesh network while reducing area overhead by 14% and incurring on an average 6.6% power penalty by boosting fault tolerance when fault rates increase. Further, our dynamic RAS scheme maintains 97.88% of network performance for real applications while incurring 20% power penalty.

Formal Proof of the Dependable Bypassing Routing Algorithm Suitable for Adaptive Networks on Chip QnoC Architecture

Approaches for the design of fault tolerant Network-on-Chip (NoC) for use in System-on-Chip (SoC) reconfigurable technology using Field-Programmable Gate Array (FPGA) technology are challenging, especially in Multiprocessor System-on-Chip (MPSoC) design. To achieve this, the use of rigorous formal approaches, based on incremental design and proof theory, has become an essential step in the validation process. The Event-B method is a promising formal approach that can be used to develop, model and prove accurately SoC and MPSoC architectures. This paper proposes a formal verification approach for NoC architecture including the dependability constraints relating to the choice of the path routing of data packets and the strategy imposed for diversion when faulty routers are detected. The formalization process is incremental and validated by correct-by-construction development of the NoC architecture. Using the concepts of graph colouring and B-event formalism, the results obtained have demonstrated its efficiency for determining the bugs, and a solution to ensure a fast and reliable operation of the network when compared to existing similar methods.

Performance Estimation of HEVC/h.265 Decoder in a Co-Design Flow with SADF-FSM Graphs

Multiprocessor System on Chip (MPSoC) technology presents an interesting solution to reduce the computational time of complex applications such as multimedia applications. Implementing the new High Efficiency Video Coding (HEVC/h.265) codec on the MPSoC architecture becomes an interesting research point that can reduce its algorithmic complexity and resolve the real time constraints. The implementation consists of a set of steps that compose the Co-design flow of an embedded system design process. One of the first anf key steps of a Co-design flow is the modeling phase which allows designers to make best architectural choices in order to meet user requirements and platform constraints. Multimedia applications such as HEVC decoder are complex applications that demand increasing degrees of agility and flexibility. These applications are usually modeling by dataflow techniques. Several extensions with several schedules techniques of dataflow model of computation have been proposed to support dynamic behavior changes while preserving static analyzability. In this paper, the HEVC/h.265 video decoder is modeled with SADF based FSM in order to solve problems of placing and scheduling this application on an embedded architecture. In the modeling step, a high-level performance analysis is performed to find an optimal balance between the decoding efficiency and the implementation cost, thereby reducing the complexity of the system. The case study in this case works with the HEVC/h.265 decoder that runs on the Xilinx Zedboard platform, which offers a real environment of experimentation.

FPGA Prototyping and Design Evaluation of a NoC-Based MPSoC

Chip communication architectures become an important element that is critical to control when designing a complex MultiProcessor System-on-Chip (MPSoC). This led to the emergence of new interconnection architectures, like Network-on-Chip (NoC). NoCs have been proven to be a promising solution to the concerns of MPSoCs in terms of data parallelism. Field-Programmable Gate Arrays (FPGA) has some perceived challenges. Overcoming those challenges with the right prototyping solutions is easy and cost-effective leading to much faster time-to-market. In this paper, we present an FPGA based on rapid prototyping in hardware/software co-design and design evaluation of a mixed HW/SW MPSoC using a NoC. A case study of two-dimensional mesh NoC-based MPSoC architecture is presented with a validation environment. The synthesis and implementation results of the NoC-based MPSoC on a Virtex 5 ML 507 enable a reasonable frequency (151.5 MHz) and a resource usage rate equals to 58% (6,586 out of 11,200 slices used).

Communication Optimizations for Multithreaded Code Generation from Simulink Models

Communication frequency is increasing with the growing complexity of emerging embedded applications and the number of processors in the implemented multiprocessor SoC architectures. In this article, we consider the issue of communication cost reduction during multithreaded code generation from partitioned Simulink models to help designers in code optimization to improve system performance. We first propose a technique combining message aggregation and communication pipeline methods, which groups communications with the same destinations and sources and parallelizes communication and computation tasks. We also present a method to apply static analysis and dynamic emulation for efficient communication buffer allocation to further reduce synchronization cost and increase processor utilization. The existing cyclic dependency in the mapped model may hinder the effectiveness of the two techniques. We further propose a set of optimizations involving repartition with strongly connected threads to maximize the degree of communication reduction and preprocessing strategies with available delays in the model to reduce the number of communication channels that cannot be optimized. Experimental results demonstrate the advantages of the proposed optimizations with 11--143% throughput improvement.

Memory-Aware Task Scheduling with Communication Overhead Minimization for Streaming Applications on Bus-Based Multiprocessor System-on-Chips

Inter-core communication introduces overheads in task schedules on Multiprocessor System-on-Chips (MPSoCs). Inter-core communication overhead not only negatively impacts the timing performance but also significantly degrades the memory usage for streaming applications running on MPSoC architectures. By minimizing inter-core communication overhead, a shorter period can be applied and system performance (e.g., throughput, memory usage) can be improved. In this paper, we focus on solving the problem of minimizing inter-core communication overhead for streaming applications on bus-based MPSoCs. The objective is to minimize inter-core communication overhead while minimizing the overall memory usage. To solve the problem, we first let tasks with intra-period data dependencies transform to inter-period data dependencies so as to overlap the execution of computation and inter-core communication tasks. By doing this, inter-core communication overhead can be effectively removed. To minimize the overall memory usage, we then perform schedulability analysis and obtain the bounds of the times needed to reschedule each task. Based on the schedulability analysis, we formulate the scheduling problem as an integer linear programming (ILP) model and obtain an optimal schedule. In addition, we propose a heuristic approach to efficiently obtain a near-optimal solution. We conduct experiments on a set of benchmarks from both real-life streaming applications and synthetic task graphs. The experimental results show that the proposed approach can significantly reduce the schedule length and improve the memory usage compared with the previous work.

A Frame work on AMBA Bus based Communication Architecture to Improve the Real Time Computing Performance in MPSoC

Enormous advancements in System-on-Chip (SoC) have led to a new area called as MPSoC, having single chip with many processors. MPSoC is usually targeted for high-end embedded designs to meet real-time requirements, where performance and bandwidth plays a major role. Multi Processor Systemon-Chip (MPSoC) deals with multiple on-chip processors and processing elements that are essential for multi-core processors integrated onto the single chip. As more and more processors are integrated onto the same silicon chip, there should be proper communication and synchronization to ensure better performance. For this purpose, several Communication Architectures (CAs) have been developed like ARM AMBA, IBM Core Connect, Altera Avalon, and Open Cores Wishbone. One of the major challenges is to select a suitable architecture among the various MPSoC architectures. AMBA bus is widely used in the highperformance and high frequency SoC designs. This paper deals with several topologies and communication protocols. In this paper AMBA versions and their buses/interfaces are discussed.

A Methodology for Invasive Programming on Virtualizable Embedded MPSoC Architectures

Exploiting the huge logic resources in current embedded devices has led to a plethora of on-chip multi-processor architec- tures. However, besides instantiating more and more soft-core processors on a chip, developing applications suited for such architectures still remains a hard task. A further step in the evolution of embedded multi-processing might be the so called Invasive Programming. In this paradigm, an application may be switched from sequential to parallel execution at runtime. A task may then dynamically invade currently unused processor resources in a multi-processor system to resume in parallel execution mode. This hardens existing problems, however, because not only the development of suited software, but also the creation of multi-processor architectures supporting this paradigm is needed. Therefore, this work presents a concise methodology to enable Invasive Programming properties on an embedded Multi-Processor System-on-Chip (MPSoC). This is achieved by combining a designer-guided code parallelization approach with a virtualizable, generic, and scalable embedded MPSoC architecture. To resolve data dependencies during task invasion, a processor-independent task-based communication scheme for the MPSoC is proposed. Moreover, a tool framework dedicated to the generic creation of virtualizable MPSoC is provided. The approach is demonstrated by the generation of an MPSoC featuring eight processors executing an application which dynamically switches at runtime between sequential and parallel execution.

A star network approach in heterogeneous multiprocessors system on chip

Multiprocessor System on Chip (MPSoC) platform plays a vital role in parallel processor architecture design. However, with the growing number of processors, interconnect on chip is becoming one of the major bottlenecks of MPSoC architecture. In this paper, we propose a star network based on peer to peer links on FPGA. The star network utilizes fast simplex links (FSL) as basic structure to connect the scheduler with heterogeneous processing elements, including processors and hardware IP cores. Blocking and nonblocking application interfaces are provided for high level programming. We built a prototype system on FPGA to evaluate the transfer time and hardware cost of the proposed star network architecture. Experiment results demonstrated that the average transfer time for each word could be reduced to 7 cycles, which achieves 14× speedup against state-of-the-art shared memory literatures. Moreover, the star network cost only 1.2 % Flip Flops and 2.45 % LUTs of a single FPGA.

A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC Architectures

Multi-Processor System-on-Chip (MPSoC) have become an essential solution for embedded applications. In this paper we focus on MPSoCs using shared-memory programming model, which facilitates the programmer task. Moreover, one of the main factors affecting the performance of such systems is the management of cache coherency problem. In this context, we propose a new cache-coherency protocol. The proposed protocol is able to dynamically adapt its functioning mode according to variations in application memory access patterns. Experimental results show that with four cores, the new protocol reduces the number of cache misses by 77%, which results in 20% reduction in execution time and 34% decrease in the total energy consumption.

Prototype Design and Synthesis of Cluster MPSoC Architecture for Multiple Applications

Modern embedded devices require high performances such as computing, throughput and power consumption. Multiprocessor System-on-Chip (MPSoC) is a promising solution to meet the requirements. And the Network-on-Chip (NoC) is used as the interconnection of MPSoC. Whereas it brings more challenge on application programming and fast design exploration of software and hardware implements automatically. In this paper we propose a cluster MPSoC architecture, which adopts hybrid interconnection of processor clusters and NoC. And we present a design automation and synthesis methodology to generate MPSoCs in a system-level way for multiple application use-cases. And it merges them onto a minimal hardware architecture of resources. The desired MPSoC design is generated with short design time, making it suited for fast design exploration for MPSoC development. The proposed design flow is implemented into a tool for Xilinx FPGAs. The experiments results illuminate that our design methodology is a convenient approach to generate the MPSoC design for multiple use-cases.

Homogeneous and Heterogeneous MPSoC Architectures with Network‐On‐Chip Connectivity for Low‐Power and Real‐Time Multimedia Signal Processing

Two multiprocessor system‐on‐chip (MPSoC) architectures are proposed and compared in the paper with reference to audio and video processing applications. One architecture exploits a homogeneous topology; it consists of 8 identical tiles, each made of a 32‐bit RISC core enhanced by a 64‐bit DSP coprocessor with local memory. The other MPSoC architecture exploits a heterogeneous‐tile topology with on‐chip distributed memory resources; the tiles act as application specific processors supporting a different class of algorithms. In both architectures, the multiple tiles are interconnected by a network‐on‐chip (NoC) infrastructure, through network interfaces and routers, which allows parallel operations of the multiple tiles. The functional performances and the implementation complexity of the NoC‐based MPSoC architectures are assessed by synthesis results in submicron CMOS technology. Among the large set of supported algorithms, two case studies are considered: the real‐time implementation of an H.264/MPEG AVC video codec and of a low‐distortion digital audio amplifier. The heterogeneous architecture ensures a higher power efficiency and a smaller area occupation and is more suited for low‐power multimedia processing, such as in mobile devices. The homogeneous scheme allows for a higher flexibility and easier system scalability and is more suited for general‐purpose DSP tasks in power‐supplied devices.

Dynamic Partial Reconfiguration Contribution on System on Programmable Chip Architecture for Motor Drive Implementation

Problem statement: Nowadays, Reconfigurable System on Chip (RSoC) shows great potential in many high performance applications that benefit from Hardware customization. Approach: In this study, we present a design approach of FPGA based Controller for electromechanical system. In this way, we present solutions obtained by Hardware/Software Code sign methodology targeted for the implementation of a motor control drive system using Multiprocessor SoC (MPSoC) architecture. In order to enhance flexibility and performance of the considered system, we design different modules of HW current controller of electronic motor. A Dynamic Partial Reconfiguration (DPR) mechanism allowing switching on the fly between those modules is described. Results: Test and validation are done to validate the approach adopted. Experimental results confirmed the efficiency of the approach and allow us to determine more recommendations that should be considered while designing a RSoC control drive system. Conclusion/Recommendations: DPR enable flexible control system hardware design. This concept allows switching between different low order controls.

Multi-Processor System-on-Chip Power Estimation Model At the CABA Level

This paper examines an approach for estimating energy consumption during the HW/SW Codesign of an embedded system. Our contribution consists on the design and the development of an energy consumption model for Multi-Processor System on Chip (MPSoC). The consumption models are integrated into System on Chip Library (SoCLib) hardware components for system co-simulation at the Cycle-Accurate Bit-Accurate (CABA) level. Experimental results show the usefulness of our model to achieve correct energy estimation for MPSoC architectures with an acceptable speed of simulations.

Networks‐on‐Chip: Architectures, Design Methodologies, and Case Studies

As the density of VLSI design increases, more processors or cores can be placed on a single chip. Therefore, the design of a Multi-Processor System-on-Chip (MP-SoC) architecture, which demands high throughput, low latency, and reliable global communication services, cannot be done by just using current bus-based on-chip communication infrastructures. Networks-on-Chip (NoC) has been proposed in recent years as a promising solution of on-chip interconnection network to provide better scalability, performance, and modularity for current and future MP-SoC architectures. The paper entitled “Networks on chips: structure and design methodologies” introduces several NoC architectures and discusses the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC. Then, a novel Bidirectional NoC (BiNoC) architecture with a dynamically self-reconfigurable bidirectional channel is presented, which can break the performance bottleneck caused by bandwidth restriction in conventional NoCs. Since buffers in on-chip networks constitute a significant proportion of the power consumption and the area of interconnects, reducing the buffer size is an important problem. The paper entitled “A buffer sizing algorithm for network on chips with multiple voltage-frequency islands” describes a two-phase algorithm to size the switch buffers in NoC in considering the support of multiple-frequency islands. The paper entitled “Self-calibrated energy-efficient and reliable channels for on-chip interconnection networks” depicts the design of an energy-efficient and reliable channel for on-chip interconnection networks (OCINs) using a self-calibrated voltage scaling technique with self-corrected green (SCG) coding scheme. Among the NoC components, links that connect the NoC routers are the most power-hungry components. The paper entitled “Intelligent on/off dynamic linkmanagement for onchip networks” presents an intelligent dynamic power management policy for NoCs with improved predictive abilities based on supervised online learning of the system status, where links are turned off and on via the use of a small and scalable neural network. Monitoring and diagnostic systems are required in modern NoC implementations to assure high performance and reliability. In the paper entitled “Status data and communication aspects in dynamically clustered network-onchip monitoring,” the design of a dynamically clustered NoC monitoring structure for traffic and fault monitoring is illustrated. Since biological organisms have better adaptability than computer systems in dealing with environmental changes or noise. A case study on the design of an evolvable neuromolecular hardware motivated from some biological evidence, which integrates interand intra-neuronal information processing, is depicted in the paper entitled “A hardware design of neuromolecular network with enhanced resolvability: a bio-inspired approach.”

A High-Level Power Model for MPSoC on FPGA

This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on FPGA. The technique is based on abstract execution profiles, called event signatures. As a result, it is capable of achieving good evaluation performance, thereby making the technique highly useful in the context of early system-level design space exploration. We have integrated the power estimation technique in a system-level MPSoC synthesis framework. Using this framework, we have designed a range of different candidate MPSoC architectures and compared our power estimation results to those from real measurements on a Virtex-6 FPGA board.