Multiply-accumulate Unit Research Articles

Low Power Transposed Form 4-Tap Finite Impulse Response Filter Using Power Efficient Multiply Accumulate Unit

Finite impulse response (FIR) filters find wide application in signal processing applications on account of the stability and linear phase response of the filter. These digital filters are used in applications, like biomedical engineering, wireless communication, image processing, speech processing, digital audio and video processing. Low power design of FIR filter is one of the major constraints that researchers are trying hard to achieve. This paper presents the implementation of a novel power efficient design of a 4-tap 16-bit FIR filter using a modified Vedic multiplier (MVM) and a modified Han Carlson adder (MHCA). The units are coded using Verilog hardware description language and simulated using Xilinx Vivado Design Suite 2015.2. The filter is synthesized for the 7-series Artix field programmable gate array with xc7a100tcsg324-1 as the target device. The proposed filter design showed an improvement of a maximum of 57.44% and a minimum of 2.44% in the power consumption compared to the existing models.

Argus CNN Accelerator Based on Kernel Clustering and Resource-Aware Pruning

Paper proposes a two-step Convolutional Neural Network (CNN) pruning algorithm and resource-efficient Field-programmable gate array (FPGA) CNN accelerator named “Argus”. The proposed CNN pruning algorithm first combines similar kernels into clusters, which are then pruned using the same regular pruning pattern. The pruning algorithm is carefully tailored for FPGAs, considering their resource characteristics. Regular sparsity results in high Multiply-accumulate (MAC) efficiency, reducing the amount of logic required to balance workloads among different MAC units. As a result, the Argus accelerator requires about 170 Look-up tables (LUTs) per Digital Signal Processor (DSP) block. This number is close to the average LUT/DPS ratio for various FPGA families, enabling balanced resource utilization when implementing Argus. Benchmarks conducted using Xilinx Zynq Ultrascale + Multi-Processor System-on-Chip (MPSoC) indicate that Argus is achieving up to 25 times higher frames per second than NullHop, 2 and 2.5 times higher than NEURAghe and Snowflake, respectively, and 2 times higher than NVDLA. Argus shows comparable performance to MIT’s Eyeriss v2 and Caffeine, requiring up to 3 times less memory bandwidth and utilizing 4 times fewer DSP blocks, respectively. Besides the absolute performance, Argus has at least 1.3 and 2 times better GOP/s/DSP and GOP/s/Block-RAM (BRAM) ratios, while being competitive in terms of GOP/s/LUT, compared to some of the state-of-the-art solutions.

Low Power and Area Efficient Borrow Save Adder for MAC Unit in VLSI Application

In hypercompetitive embedded system environment, to develop the unique characteristic of machine learning computation for more efficient MAC design for reduced both the area and power. In this paper, Multiply–accumulate (MAC) computations account for a large part of machine learning accelerator operations use in pipelined structure is usually adopted to improve the performance by reducing the number of adder circuits. The proposed a pipelining method that eliminates some of the flip-flops in carry look adder in selectively. Here, introduce the applying the Feed forward-Cutset-Free (FCF) pipelining method in borrow save adder (BSA) to the accumulator by reducing the design, optimized the power dissipation and undesired data transition in (MFCF-PA). From the FPGA Xilinx simulation output result shows that, the MAC unit reached between 15% and 25% energy saving and area reduction of 15% over the existing carry look ahead adder (CLA) conformist pipelined MAC units.

Optimizing Convolutional Neural Network Accelerator on Low-Cost FPGA

Convolutional neural network (CNN) is one of the most promising algorithms that outweighs other traditional methods in terms of accuracy in classification tasks. However, several CNNs, such as VGG, demand a huge computation in convolutional layers. Many accelerators implemented on powerful FPGAs have been introduced to address the problems. In this paper, we present a VGG-based accelerator which is optimized for a low-cost FPGA. In order to optimize the FPGA resource of logic element and memory, we propose a dedicated input buffer that maximizes the data reuse. In addition, we design a low resource processing engine with the optimal number of Multiply Accumulate (MAC) units. In the experiments, we use VGG16 model for inference to evaluate the performance of our accelerator and achieve a throughput of 38.8[Formula: see text]GOPS at a clock speed of 150[Formula: see text]MHz on Intel Cyclone V SX SoC. The experimental results show that our design is better than previous works in terms of resource efficiency.

High Level Synchronization and Computations of Feed Forward Cut-Set based Multiply Accumulate Unit

In a modern technology-based application, digital signal processing (DSP) is a major priority one, in this gadgets application, the Multiply Accumulate Unit (MAC) will occupy more memory usages, power consumptions and critical path delay. Due to the number of arithmetic operations, this MAC unit will play’s a major role in this application product. Thus, the pipelined based architecture will be used to reduce the number of critical paths delay and to improve the performance of MAC architecture. However, the number of flip flops will be increased in the MAC unit, due to number of pipelined architectures. Consequently, it will increase the area and the power consumption. Thus, proposed work of this paper will get a novelty process of feed forward cut-set based MAC architecture with high level synchronization of XOR-MUX full adder with compressor technique. It will reduce the number of logic gates in MAC architecture and hence prove the performance in FPGA Implementation of LUT based area, critical path delay and average power consumption.

A Novel Approach to Develop Low Power MACs for 2D Image Filtering

In emerging technologies, a vital role is played by ASIC designs in processor operations. There is a necessity to develop such a processor composed of low power blocks. This paper discusses the design exploration of the fixed-point multiply-accumulate unit to achieve high-speed and low power consumption. A 2D image convolution process is developed by stacking and combining several MAC blocks. The developed MAC comprises a sequential multiplier, controller, and optimized adder units. The entering image pixels and kernel pixels are checked for similarity and accordingly isolated by the controller unit, thereby saving power by eliminating the redundant multiplications. A novel idea of reducing the additions in image filtering operations is incorporated in the design. The performance of the proposed MAC showed a 28% power reduction compared to the conventional approaches.

A Method of Increasing Digital Filter Performance Based on Truncated Multiply-Accumulate Units

This paper proposes new digital filter architecture based on a modified multiply-accumulate (MAC) unit architecture called truncated MAC (TMAC), with the aim of increasing the performance of digital filtering. This paper provides a theoretical analysis of the proposed TMAC units and their hardware simulation. Theoretical analysis demonstrated that replacing conventional MAC units with modified TMAC units, as the basis for the implementation of digital filters, can theoretically reduce the filtering time by 29.86%. Hardware simulation showed that TMAC units increased the performance of digital filters by up to 10.89% compared to digital filters using conventional MAC units, but were associated with increased hardware costs. The results of this research can be used in the theory of digital signal processing to solve practical problems such as noise reduction, amplification and suppression of the frequency spectrum, interpolation, decimation, equalization and many others.

An Error Compensation Technique for Low-Voltage DNN Accelerators

Reducing supply voltages of deep neural network (DNN) accelerators has been of particular interest since it can achieve high energy efficiency for mobile/edge applications. To ensure reliable DNN operations at low voltage, improving the timing error resilience of DNN accelerator is highly required. In this article, we present an error resilient technique to support low-voltage DNN operations by detecting and compensating erroneous computations using the proposed compensation multiply-accumulate (CMAC) unit. First, the timing errors are detected using Razor flip-flops at critical data-path, and erroneous computations are identified and dumped. Using additional multiplier data-path with flip-flops, the dropped computations are compensated in the next CMAC unit without additional clock-cycle penalty. Various bit-precisions of error compensations are analyzed to efficiently tradeoff DNN accuracy and hardware overhead. To improve the DNN accuracy even at low bit-precision of compensation, two types of rounding techniques are presented to effectively reflect the actual distribution of DNN computation results. The low-voltage DNN accelerator based on the proposed error compensation scheme has been implemented using 65-nm CMOS. Post-layout simulations show that the proposed DNN accelerator for ResNet-18 achieves about 47% and 24% energy savings compared with baseline and state-of-the-art error resilient DNN accelerators, respectively.

Weight-Oriented Approximation for Energy-Efficient Neural Network Inference Accelerators

Current research in the area of Neural Networks (NN) has resulted in performance advancements for a variety of complex problems. Especially, embedded system applications rely more and more on the utilization of convolutional NNs to provide services such as image/audio classification and object detection. The core arithmetic computation performed during NN inference is the multiply-accumulate (MAC) operation. In order to meet tighter and tighter throughput constraints, NN accelerators integrate thousands of MAC units resulting in a significant increase in power consumption. Approximate computing is established as a design alternative to improve the efficiency of computing systems by trading computational accuracy for high energy savings. In this work, we bring approximate computing principles and NN inference together by designing NN specific approximate multipliers that feature multiple accuracy levels at run-time. We propose a time-efficient automated framework for mapping the NN weights to the accuracy levels of the approximate reconfigurable accelerator. The proposed weight-oriented approximation mapping is able to satisfy tight accuracy loss thresholds, while significantly reducing energy consumption without any need for intensive NN retraining. Our approach is evaluated against several NNs demonstrating that it delivers high energy savings (17.8% on average) with a minimal loss in inference accuracy (0.5%).

Monolithic 3D stacked multiply-accumulate units

The monolithic 3D stacking (M3D) reduces the critical path delay, leveraging 1) short latency of a monolithic inter-tier via (MIV) and 2) short 2D interconnect and cell delay through smaller footprint. In this paper, we propose M3D stacked multiply-accumulate (MAC) units; MAC units have a relatively large number of long wires. With the Samsung 28 nm ASIC library, the M3D stacked MAC units reduce the critical path delay by up to 28.9%, compared to the conventional 2D structure. In addition, the M3D stacked MAC units reduce dynamic energy and leakage power by up to 9.6% and 21.7%, respectively. Compared to the TSV stacked MAC units, the M3D stacked MAC units consume less dynamic energy and leakage power by up to 37.1% and 73.6%, respectively. Though the 3D stacking technology inevitably causes higher peak temperature than the 2D structure, our thermal results show that the peak temperature of the M3D stacking is always lower than that of the TSV-based 3D stacking. Furthermore, when the size of the MAC unit is optimized in convolutional neural network (CNN) applications, the peak temperature of the M3D stacking is 88.3 °C at most, which is still under the threshold temperature.

A low-power asynchronous hardware implementation of a novel SVM classifier, with an application in a speech recognition system

Machine Learning (ML) has been applied in so many areas in reason of its robustness, usability, and reliability, mainly in hardware implementation. One of its well-known algorithms is the Support Vector Machine (SVM), the simplest to be applied in hardware because of its mathematical modeling. In this study, we propose the implementation in hardware of SVM multi-class classifiers within the asynchronous paradigm (i.e., without clock signal application) in a 4-stage pipeline architecture. With the purpose to evaluate the proposed architecture behavior, we used a Field Programmable Gate Array (FPGA) device to prototype the circuit. The proposed asynchronous SVM classifier is applied in a Speech Recognition system of 30 classes where a hybrid training algorithm was processed in the Matlab software, known as PSO-SVM training algorithm. Therefore, the training phase was processed in software in reason of its computational load. For the SVM classification phase, we propose, for the first time to the best of our knowledge, an asynchronous pipeline architecture of four stages with Multiply-Accumulator (MAC) unit application and three different control circuits described from Extended Burst-Mode (XBM) and State Transition Graph (STG) specifications, leading to energy-efficient design. In order to validate the SVM recognition results in the speech recognition application, the tests are from 60 speeches and 20 speakers, so it is a diversified and reliable data set of tests. The main goal here was to design a machine learning hardware implementation in a low power application and, through that, to prove that the asynchronous paradigm reduced power. As a result, we obtained a reduced power consumption of 5.72 mW, a fast average response time which was 0.61μs and the most area-efficient circuit (1315 LUTs); the accuracy in recognition success rate was another preoccupation, and it was very successful, 98% of success. Besides, we present comparisons with an asynchronous version of the same SVM datapath and with different synchronous architectures from literature to prove that our novelty is better in power consumption and area size. For hardware applications where low power and high performance are the sought features, the presented architecture revealed the best position when compared to similar works from the recent technical literature for pattern recognition systems.

Computationally-Efficient Algorithm for Real-Time Absence Seizure Detection in Wearable Electroencephalography.

Advances in electroencephalography (EEG) equipment now allow monitoring of people with epilepsy in their daily-life environment. The large volumes of data that can be collected from long-term out-of-clinic monitoring require novel algorithms to process the recordings on board of the device to identify and log or transmit only relevant data epochs. Existing seizure-detection algorithms are generally designed for post-processing purposes, so that memory and computing power are rarely considered as constraints. We propose a novel multi-channel EEG signal processing method for automated absence seizure detection which is specifically designed to run on a microcontroller with minimal memory and processing power. It is based on a linear multi-channel filter that is precomputed offline in a data-driven fashion based on the spatial-temporal signature of the seizure and peak interference statistics. At run-time, the algorithm requires only standard linear filtering operations, which are cheap and efficient to compute, in particular on microcontrollers with a multiply-accumulate unit (MAC). For validation, a dataset of eight patients with juvenile absence epilepsy was collected. Patients were equipped with a 20-channel mobile EEG unit and discharged for a day-long recording. The algorithm achieves a median of 0.5 false detections per day at 95% sensitivity. We compare our algorithm with state-of-the-art absence seizure detection algorithms and conclude it performs on par with these at a much lower computational cost.

Error Probability Models for Voltage-Scaled Multiply-Accumulate Units

Energy efficiency is a critical design objective in deep learning hardware, particularly for real-time machine learning applications where the processing takes place on resource-constrained platforms. The inherent resilience of these applications to error makes voltage scaling an attractive method to enhance efficiency. Timing error probability models are proposed in this article to better understand the effects of voltage scaling on error rates and power consumption of multiply-accumulate units. The accuracy of the proposed models is demonstrated via Monte Carlo simulations. These models are then used to quantify the related tradeoffs without relying on time-consuming hardware-level simulations. Both modern FinFET and emerging tunneling field-effect transistor (TFET) technologies are considered to explore the dependence of the effects of voltage scaling on these two technologies.

High-Bandwidth Spatial Equalization for mmWave Massive MU-MIMO With Processing-in-Memory

All-digital basestation (BS) architectures enable superior spectral efficiency compared to hybrid solutions in massive multi-user MIMO systems. However, supporting large bandwidths with all-digital architectures at mmWave frequencies is challenging as traditional baseband processing would result in excessively high power consumption and large silicon area. The recently-proposed concept of finite-alphabet equalization is able to address both of these issues by using equalization matrices that contain low-resolution entries to lower the power and complexity of high-throughput matrix-vector products in hardware. In this brief, we explore two different finite-alphabet equalization hardware implementations that tightly integrate the memory and processing elements: (i) a parallel array of multiply-accumulate (MAC) units and (ii) a bit-serial processing-in-memory (PIM) architecture. Our all-digital VLSI implementation results in 28nm CMOS show that the bit-serial PIM architecture reduces the area and power consumption up to a factor of $ 2\times $ and $3\times $ , respectively, when compared to a parallel MAC array that operates at the same throughput.

A High-Accuracy Hardware-Efficient Multiply–Accumulate (MAC) Unit Based on Dual-Mode Truncation Error Compensation for CNNs

This paper presents a multiply–accumulate (MAC) unit that enables a dual-mode truncation error compensation (TEC) scheme based on a fixed-width Booth multiplier (FWBM) for convolutional neural network (CNN) inference operations. The proposed tailored TEC schemes of Modes 1 and 2 can achieve high MAC accuracy for a general or rectified linear unit-based CNN model with general (Mode 1) or positive/zero (Mode 2) input patterns. By pre-calculating the pre-known CNN model coefficients, the proposed dual-mode TEC scheme can be realized using minimal partial product operations with high hardware efficiency using a software–hardware codesign approach. Further, a reconfigurable architecture of the resultant MAC unit is presented to realize the proposed dual-mode TEC scheme. By evaluating the accuracy for 9- $N$ and 25- $N$ MAC operations ( $N$ denotes the number of times MAC is performed), a MAC operation using the proposed TEC scheme can achieve the highest accuracy for Modes 1 and 2, relative to contrast samples that directly employ the FWBM with a conventional TEC function. The hardware performances of 9- $N$ and 25- $N$ MAC units are also evaluated using the TSMC 40-nm standard cell library. Compared with the contrast TEC-enabled designs, the proposed MAC unit exhibits higher hardware efficiency in terms of area, delay, and power consumption and achieves a minimum reduction of more than 40% in both area-delay-error and power-delay-error products. Moreover, the resultant 9- $N$ and 25- $N$ MAC units are verified using a system-on-chip field-programmable gate array platform to test a CNN model for handwritten digit classification.

Comparative performance analysis of FPGA-based MAC unit using non-conventional number system in TVL domain for signal processing algorithm

Today, the complication of binary digital hardware system is progressively growing. Due to this fact, new methodologies for efficiently describing and realising the digital systems are explored in this paper. Multi-valued logic methodology offers a few preferences over existing binary digital system. One of the well-known multi-valued logic systems is ternary value logic (TVL) system. It is seen that all kind of digital signal processing (DSP) algorithms widely use multiply-accumulate (MAC) operation for superior digital processing system. To implement high performance DSP algorithms MAC unit is used extensively. In current scenario, it is seen that non-conventional, non-binary number system-based architecture is also exhibited better performance. The example of such non-conventional, non-binary number systems is ternary residue number systems (TRNSs) and double base ternary number system (DBTNS). Here, a comparative study is made on performance analysis of MAC unit using various non-conventional, non-binary number system. All the architecture is mapped on FPGA for analysis its performance.

Comparative performance analysis of FPGA-based MAC unit using non-conventional number system in TVL domain for signal processing algorithm

Today, the complication of binary digital hardware system is progressively growing. Due to this fact, new methodologies for efficiently describing and realising the digital systems are explored in this paper. Multi-valued logic methodology offers a few preferences over existing binary digital system. One of the well-known multi-valued logic systems is ternary value logic (TVL) system. It is seen that all kind of digital signal processing (DSP) algorithms widely use multiply-accumulate (MAC) operation for superior digital processing system. To implement high performance DSP algorithms MAC unit is used extensively. In current scenario, it is seen that non-conventional, non-binary number system-based architecture is also exhibited better performance. The example of such non-conventional, non-binary number systems is ternary residue number systems (TRNSs) and double base ternary number system (DBTNS). Here, a comparative study is made on performance analysis of MAC unit using various non-conventional, non-binary number system. All the architecture is mapped on FPGA for analysis its performance.

High-Performance Digital Filtering on Truncated Multiply-Accumulate Units in the Residue Number System

The article proposes new modified Multiply-Accumulate (MAC) units called truncated MAC units and using residue number system (RNS) with moduli of a special form. The effectiveness of the proposed blocks is verified by hardware implementation of digital filtering. The paper presents a comparative theoretical analysis of the proposed approach using the RNS and the known methods using the conventional positional number system (PNS) and RNS. Moreover, in the paper, a hardware simulation on FPGA of digital filters using arithmetic of RNS is performed, and comparison with the known implementations are realized. It is shown that using proposed approach based on RNS makes it possible to increase the frequency of digital filters by about 4 times, and reduce the hardware costs by 3 times, in comparison with the use of the traditional positional number system. Comparison proposed method and known methods based on RNS shows that using proposed method allows to increase the frequency by about 2-6 times, and reduce the hardware costs by 1.5-5 times, with increasing power consumption by 23%. Obtained results open up the possibility for efficient hardware implementation of digital filters on modern devices (FPGA, ASIC, etc.) for solving practical problems such as noise reduction, amplification and suppression of frequencies, interpolation, decimation, equalization, and many others.

A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations Into Partial Product Reduction Process

In this paper, we propose a low-power high-speed pipeline multiply-accumulate (MAC) architecture. In a conventional MAC, carry propagations of additions (including additions in multiplications and additions in accumulations) often lead to large power consumption and large path delay. To resolve this problem, we integrate a part of additions into the partial product reduction (PPR) process. In the proposed MAC architecture, the addition and accumulation of higher significance bits are not performed until the PPR process of the next multiplication. To correctly deal with the overflow in the PPR process, a small-size adder is designed to accumulate the total number of carries. Compared with previous works, experimental results show that the proposed MAC architecture can greatly reduce both power consumption and circuit area under the same timing constraint.

McDRAM v2: In-Dynamic Random Access Memory Systolic Array Accelerator to Address the Large Model Problem in Deep Neural Networks on the Edge

The energy efficiency of accelerating hundreds of MB-large deep neural networks (DNNs) in a mobile environment is less than that of a server-class big chip accelerator because of the limited power budget, silicon area, and smaller buffer size of static random access memory associated with mobile systems. To address this challenge and provide powerful computing capability for processing large DNN models in power/resource-limited mobile systems, we propose McDRAM v2, which is a novel in-dynamic random access memory (DRAM) systolic array accelerator architecture. McDRAM v2 makes the best use of large in-DRAM bandwidths for accelerating various DNN applications. It can handle large DNN models without off-chip memory accesses, in a fast and efficient manner, by exposing the large DRAM capacity and large in-DRAM bandwidth directly to an input systolic array of a processing element matrix. Additionally, it maximizes data reuse using a systolic multiply-accumulate (MAC) structure. The proposed architecture maximizes the utilization of large-scale MAC units by judiciously exploiting the DRAM's internal bus and buffer structure. An evaluation of large DNN models in the fields of image classification, natural language processing, and recommendation systems shows that it achieves 1.7 times tera operations per second (TOPS), 3.7 times TOPS/watt, and 8.6 times TOPS/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> improvements over a state-of-the-art mobile graphics processing unit accelerator, and 4.1 times better energy efficiency over a state-of-the-art server-class accelerator. Moreover, it incurs a minimal overhead, i.e., a 9.7% increase in area, and uses less than 4.4 W of peak operating power.