Multiplier-less Architecture Research Articles

FPGA implementation of compact and low-power multiplierless architectures for DWT and IDWT

FPGA implementation of compact and low-power multiplierless architectures for DWT and IDWT

Optimal Adder-Multiplexer Co-Optimization for Time-Multiplexed Multiplierless Architectures

Optimal Adder-Multiplexer Co-Optimization for Time-Multiplexed Multiplierless Architectures

ARCHITECTURAL DESIGN AND OPTIMIZATION OF DISTRIBUTED ARITHMETIC BASED 2-D DISCRETE COSINE TRANSFORM

DCT is immensely used in Multimedia applications because it provides high energy compaction. The proposed architectural design of 1D-DCT employs an efficient computational technique, Distributed arithmetic and is synthesized using front end VLSI technique. The motive of utilising Distributed arithmetic is to have multiplier-less architecture that reduces the Area-delay product in comparison to the multiplier-based design by retaining the same structural regularities. The symmetric property of the DCT kernel matrix is applied to develop the proposed architecture which reduces the requirements of a number of multiplications by almost 50%. The 1D-DCT architecture is extended to 2D-DCT using only N 1D-DCT modules, while the conventional row-column decomposition method requires 2N 1D-DCT modules. The proposed 2D-DCT architecture is designed and implemented on a 65nm LX110T device of Vertex-5 FPGA and its performance evaluation is carried out. The debug and verification process has been carried out using the Virtual input-output technique. The results show improvement in delay and area consumption in contrast with existing models.

Memory-efficient architecture for FrWF-based DWT of high-resolution images for IoMT applications

This paper proposes a simple low memory architecture for computing discrete wavelet transform (DWT) of high-resolution (HR) images on low-cost memory-constrained sensor nodes used in visual sensor networks (VSN) or Internet of Multimedia Things (IoMT). The main feature of the proposed architecture is the novel data scanning technique that makes memory requirement independent of the image size. The proposed architecture needs only (30S) words of memory, where S is the number of parallel processing units and a critical path delay (CPD) equal to the delay of a multiplier (Tm). Furthermore, a multiplierless version of this architecture is also proposed which reduces the CPD to Ta<Tm (where Ta is the delay of an adder). In order to evaluate their effectiveness, the proposed architectures are coded in HDL and implemented on same FPGA board. Their performance is also compared with other state-of-the-art low memory DWT architectures. The experimental results show the superiority of the proposed architectures in terms of memory and CPD compared to existing DWT architectures. Moreover, the reduction in CPD to Ta indicates that the operating frequency can be scaled up by several factors and can be chosen depending upon the application. Compared to one of the best state-of-the-art DWT architecture, proposed multiplierless architecture (with S = 4) needs 57.37% less LUT’s and 64.39% less flip-flops for HR image of dimension 2048 × 2048. Moreover, the proposed architecture needs no LUTRAM and DSP, whereas the existing architecture requires 3264 LUTRAM and 24 DSP’s. Thus the proposed multiplierless architecture is superior to the existing state-of-the-art architecture and is suitable for IoMT/VSNs.

Coefficient Combined and Shift and ADD Implementation (CSSI) Based Tunable Multiplierless Rotator Design

Signal processing algorithms like Discrete Fourier Transform, Discrete Cosine Transform, and Fast Fourier Transform Transforms find various applications in the field of Image processing, Wireless communication, Robotics, and many others. It covers basically three operations viz. Multiply, Shift and Accumulate. Hence if the input data goes on rising as in cases where high resolution is required the amount of multiply operations also rises significantly. For example the number of complex multiply operations in case of Discrete Fourier Transform is N2, where N is the number of points. Latency becomes an important issue which needs to be addressed in today’s era as we, humans, thrive for the fastest systems with maximum resolution. To reduce latency we need to either emphasize on reduction in amount of data to be processed or change the processing structure which can affect the overall time to output. Multiplierless techniques for this purpose has been always a research area as it helps in reduction of the later part. Coordinate rotation of digital computer (CORDIC) based techniques are well known for the Multiplierless implementation of the sinusoids. However it carries certain drawbacks viz. large number of iterations and accuracy. This paper provides Coefficient combined &amp; shift and add implementation (CCSSI) based approach for the design of Multiplierless rotators for various transforms for multiple constant rotators as well. The approach improves the range of coefficients with respect to number of adders (the range taken is from 4 to 10 adders) and number of point (the range taken is from 1 to 64 points) compared to the existing approaches and is shown in the results. It also presents a novel tunable Multiplierless architecture.

An Efficient FPGA Realization of Seizure Detection from EEG Signal Using Wavelet Transform and Statistical Features

Abnormal electrical activity of a group of brain cells is known as seizure. Electroencephalogram (EEG) is most commonly used for the detection of seizure. This paper presents an efficient method for seizure detection from EEG signal using wavelet transform and statistical features in Field Programmable Gate Array (FPGA). A hardware efficient multiplierless architecture of 3/5 B-Spline wavelet transform is used for subband decomposition. Variance, standard deviation, mean energy, maximum amplitude, skewness, and kurtosis are the various features analyzed. There is a significant difference in the feature values obtained from EEG database of patient and a normal individual. The classifier used to classify the selected features is support vector machine classifier. Confusion matrix is used for measuring the accuracy of the proposed classifier. The system has two phases named training phase and testing phase. In order to train the system in the training phase EEG database of both epileptic seizure affected and normal individual is given. In the testing phase, the system will detect the presence or absence of seizure in the inputted EEG database. It is possible to fully place and route the detection system in an FPGA. The system is verified by Verilog in ISim simulator and synthesized in Virtex 6.

FPGA-Based Hardware Architecture for Fuzzy Homomorphic Enhancement Based on Partial Differential Equations

This paper presents an efficient, high speed hardware architecture for a PDE-based variational fuzzy homomorphic color image enhancement algorithm for both RGB and HSI/HSV color space variants. The developed architecture avoids the use of filters either in the spatial or frequency domain, utilizing an easily implementable fuzzy membership function with a high boost emphasis filter characteristic. This eliminates multiply-accumulate (MAC) operations, which result in increased usage of hardware resources, especially in smaller FPGA devices where multipliers are costly. The resulting implemented multiplier-less architecture yields a soft filtering effect due to the fuzzy evaluation when compared with the hard and crisp homomorphic filters based in the frequency and spatial domain. Based on the device utilization information obtained from hardware synthesis, the fuzzy homomorphic algorithm is shown to be the least computationally complex and faster algorithm. Additionally, the proposed architecture consumes the least amount of hardware resources on the target FPGA when compared with the spatial domain homomorphic filter. This reduced hardware structural and computational complexity makes the system easily incorporated within a PDE-based framework for improved results, which enables gradual but controlled illumination correction. The results show that the proposed system is a more effective and versatile enhancement system than those found in the literature.

FPGA-Based Multiplier-Less Log-Based Hardware Architectures for Hybrid Color Image Enhancement System

Logarithmic image processing (LIP) models provide a viable framework for image enhancement, particularly the color-based models. These techniques, due to their vector nature, avoid the problems of grayscale methods applied to RGB color image processing. Furthermore, the absence of multiply-accumulate (MAC) operations makes them amenable to hardware realization for faster operation when compared with spatial filter kernel-based approaches. However, details of image scenes are not always revealed after processing and homomorphic filters are still a popular low-complexity option for correction of images acquired under uneven illumination conditions, notwithstanding the fading that occurs when processing RGB color images. Though nonlinear color space converter hardware architectures have been implemented and reported in the literature for improving results from conventional illumination correction techniques, they add to the hardware complexity. The contributions of the work described in this paper includes original, practical, standard and logarithmic, multiplier-less high-speed architectures for a variant of the LIP model in addition to standard and log-hybrid architectures for a modified spatial homomorphic filter (MSDHF) to reduce color fading in RGB space. The modified homomorphic filter is able to enhance both faded/bright and dark low-contrast images, giving it an edge over standard illumination correction systems. A combined approach utilizing the MSDHF and simplified LIP algorithms enhances the strengths of the individual algorithms while minimizing their individual weaknesses. Comparisons of the developed systems are made with the standard homomorphic filter architecture and similar works from the literature.

Design of new selective CIC filter functions with passband‐droop compensation

The main aim of this reported work was to design new selective cascaded-integrator-comb (CIC) filter functions. The theoretical design equations and impulse response coefficients, as well as the frequency response characteristics of the novel filter functions are presented. Compared with existing filter functions in the literature, the proposed functions not only have improved insertion loss but also a multiplierless architecture, better passband characteristics and lower impulse response coefficients.

Design of two-stage nonrecursive rotated comb decimation filters with droop compensation and multiplierless architecture

This paper proposes a class of decimation filters with reduced passband signal distortion and improved spurious signal rejection across the folding bands. These filters are well-suited to decimation of oversampled digital signals processed by wideband digital receivers and ΣΔ AD converters. The total decimation factor is split between two stages of decimation and zero rotation in a nonrecursive form is applied at the lower rate in order to reduce the computational complexity of the proposed filters. We also address a framework to implement multiplierless filters and to compensate for the passband droop introduced by this class of filters. For increased flexibility, we generalize the transfer function by allowing different orders between the two stages of decimation.The paper presents many examples to clearly describe the design procedure. Comparisons are also given with the goal of contrasting the magnitude responses of the proposed filters with the ones of three other techniques recently proposed in the literature, as well as with classical comb filters.

Precise VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet Filter Banks With Low Adder-Count

A multiplier-less architecture based on algebraic integer representation for computing the Daubechies 6-tap wavelet transform for 1-D/2-D signal processing is proposed. This architecture improves on previous designs in a sense that it minimizes the number of parallel 2-input adder circuits. The algorithm was achieved using brute-force numerical optimization of the algebraic integer representation. The proposed architecture furnishes exact computation up to the final reconstruction step, which is the operation that maps the exactly computed filtered results from algebraic integer representation to fixed-point. Compared to our recent work, this architecture shows a reduction of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$27\cdot n-16$</tex></formula> adder circuits, where <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$n$</tex> </formula> is the number of wavelet decomposition levels. The design is physically implemented for a 4-level 1-D/2-D decomposition using a Xilinx Virtex-6 vcx240t-1ff1156 field programmable gate array (FPGA) device operating at up to a maximum clock frequency of 344/ 168 MHz. The FPGA implementation of 1-D/2-D are tested using hardware co-simulation using an ML605 board with clock of 100 MHz. A 45 nm CMOS synthesis of 2-D designs show improved clock frequency of better than 306 MHz for a supply voltage of 1.1 V.

AUTOMATIC DESIGN OF SHIFT-AND-ADD BASED COLOR SPACE CONVERTER USING A GENETIC ALGORITHM

The main purpose of this paper is to investigate a novel design method using a genetic algorithm (GA) to automatically evolve the multiplierless CSC circuit architecture. In order to demonstrate the effectiveness of the described design method, several test images are adopted respectively to perform RGB to YCbCr color conversion experiment. The experimental results represent that the performance of the implemented hardware architecture is good when carrying out color space conversion from RGB to YCbCr. It also has the advantage of being high-speed, low-complexity, and low-area.

Algebraic integer architecture with minimum adder count for the 2-D Daubechies 4-tap filters banks

A multiplierless architecture based on algebraic integer representation for computing the Daubechies 4-tap wavelet transform for 1-D/2-D signal processing is proposed. This architecture improves on...

An improved class of multiplierless decimation filters: Analysis and design

In this paper, we present a class of low-complexity decimation filters for oversampled discrete-time signals. The proposed class of filters improves the frequency response of classical comb filters in two respects. First, it introduces extra-attenuation around the so-called folding bands, i.e., frequency intervals whose spurious signals are folded down to baseband during the decimation process. Second, this class reduces the passband distortion via an effective droop-compensator block, thus increasing the passband of the decimation filters. Like comb filters, the proposed class can be realized through multiplierless architectures, which are also discussed thoroughly in the paper. Unlike comb filters, the proposed filters have superior spurious signal rejection and a greatly reduced droop in the signal passband. These features make the proposed filters suitable for multistage decimation applications, such as reconfigurable software radio receivers, as well as for decimating oversampled digital signals produced by @[email protected] A/D converters. The paper discusses several useful techniques for designing the proposed filters in a variety of architectures with emphasis on non-recursive architectures. Design examples are discussed to highlight the key frequency features along with implementation issues aimed at reducing the computational complexity of the filters.

Improved number plate localisation algorithm and its efficient field programmable gate arrays implementation

Number plate localisation is a very important stage in an automatic number plate recognition (ANPR) system and is computationally intensive. This study presents a low complexity with high-detection rate number plate localisation algorithm based on morphological operations together with an efficient multiplier-less architecture based on that algorithm. The proposed architecture has been successfully implemented and tested using a Mentor Graphics RC240 FPGA (field programmable gate arrays) development board equipped with a 4M-gate Xilinx Virtex-4 LX40. Two database sets sourced from the UK and Greece and including 1000 and 307 images, respectively, both with a resolution of 640 × 480, have been used for testing. Results achieved have shown that the proposed system can process an image in 4.7 ms, while achieving a 97.8% detection rate and consuming only 33% of the available area of the FPGA.

Design of a shift-and-add based hardware accelerator for color space conversion

In this paper, a Nios II processor based hardware/software co-design architecture with high expandability and development flexibility is proposed. The architecture integrates a pipelined color space converter (CSC), hardware accelerator (HA), and a LCD touch module (LTM) HA, which facilitates a high-speed implementation of RGB to YCbCr color space conversion with a real-time image display. To avoid the inefficiency of CSC circuit architecture due to massive floating-point multiplication operations in the conversion formulae, a GA-based evolutionary technique is used to realize the fast multiplierless CSC hardware architecture. Meanwhile, a pipeline design method is further applied to enhance the maximum operating frequency in circuit design. As compared to the commonly used floating-point based CSC architecture, the pipelined CSC HA in this paper has excellent advantages of low-complexity and high speed. After the mechanism is integrated into a system-on-a-programmable-chip (SOPC), the maximum operating frequency reached 168.12 MHz. That is, in every 0.11 s, the color space conversion can process a 512 × 512 image. This excellent result is practical to the fast development of different kind of image/video processing systems.

An Efficient Genetic Encoding Scheme for Multiplierless Color Space Converter Design

Color space conversion has become a very important role in image and video processing systems. To speed up some processing processes, many communication and multimedia video compression schemes use luminance-chrominance type color spaces, such as YCbCr or YUV, making a mechanism for converting between different formats necessary. Therefore, techniques which efficiently implement this conversion are desired. For the recent years, a new field of research called Evolvable Hardware (EHW) has emerged which combines aspects of evolutionary computation with hardware design and synthesis. It is a new scheme inspired by natural evolution, for automatic design of hardware systems. This paper presents a novel evolutionary approach for efficient implementation of a RGB to YCbCr color space converter suitable for Field Programmable Gate Array (FPGAs) and VLSI. In the proposed method, we use the genetic algorithm to automatically evolve the multiplierless architecture of the color space converter. The architecture employs only a few shift and addition operations to replace the complex multiplications. The experimental results represent that the performance of implemented architecture is good at RGB to YCbCr color space converting, and it also has the advantages of high-speed, low-complexity, and low-area.

Low Power R4SDC Pipelined FFT Processor Architecture

When the real-time signal processing is required pipelined FFT is the suitable option because of its high throughput and low power demands. A number of FFT architectures are there. Radix-4 single delay commutator (R4SDC) architecture is researched in this paper. R4SDC is the most popular pipeline FFT architectures, because of its efficient use of butterflies and multipliers. In this a low power technique for the pipeline FFT architecture is discussed. In this, Conventional R4SDC architecture, complex multiplier, and multiplier-less architecture based on common sub-expression technique are implemented and compared for 16, 64 and 256-point FFT architectures. A new type of multiplier algorithm called Multiplier-less architecture is implemented and compared with the carry save array, Wallace and Conventional complex multiplier (NBW).

Optimization and implementation of scaling-free CORDIC-based direct digital frequency synthesizer for body care area network systems.

Coordinate rotation digital computer (CORDIC) is an efficient algorithm for computations of trigonometric functions. Scaling-free-CORDIC is one of the famous CORDIC implementations with advantages of speed and area. In this paper, a novel direct digital frequency synthesizer (DDFS) based on scaling-free CORDIC is presented. The proposed multiplier-less architecture with small ROM and pipeline data path has advantages of high data rate, high precision, high performance, and less hardware cost. The design procedure with performance and hardware analysis for optimization has also been given. It is verified by Matlab simulations and then implemented with field programmable gate array (FPGA) by Verilog. The spurious-free dynamic range (SFDR) is over 86.85 dBc, and the signal-to-noise ratio (SNR) is more than 81.12 dB. The scaling-free CORDIC-based architecture is suitable for VLSI implementations for the DDFS applications in terms of hardware cost, power consumption, SNR, and SFDR. The proposed DDFS is very suitable for medical instruments and body care area network systems.

Approximation Method for High Speed Multiplier-Less Dwt Architecture

This paper presents a VLSI design approach for a high speed and real time Discrete Wavelet Transform computing. The hardware requirement is a major concern in the computation of discrete wavelet transform. There are many multiplier-less architecture for DWT for reducing the hardware requirement. But it is observed that the approximation method for constant multiplier implementation in DWT can increases the speed and reduces the hardware requirement for the computation of Discrete Wavelet Transform. Keywords - DWT, BBRF, Fast-convolution, Lifting.