Multiple-valued Current-mode Circuits Research Articles

Logic-In-Control-Architecture-Based Reconfigurable VLSI Using Multiple-Valued Differential-Pair Circuits

A fine-grain bit-serial multiple-valued reconfigurable VLSI based on logic-in-control architecture is proposed for effective use of the hardware resources. In logic-in-control architecture, the control circuits can be merged with the arithmetic/logic circuits, where the control and arithmetic/logic circuits are constructed by using one or multiple logic blocks. To implement the control circuit, only one state in a state transition diagram is allocated to one logic block, which leads to reduction of the complexity of interconnections between logic blocks. The fine-grain logic block is implemented based on multiple-valued current-mode circuit technology. In the fine-grain logic block, an arbitrary 3-variable binary function can be programmed by using one multiplexer and two universal literal circuits. Three-variable binary functions are used to implement the control circuit. Moreover, the hardware resources can be utilized to construct a bit-serial adder, because full-adder sum and carry can be realized by programming in the universal literal circuit. Therefore, the logic block can be effectively reconfigured for arithmetic/logic and control circuits. It is made clear that the hardware complexity of the control circuit in the proposed reconfigurable VLSI can be reduced in comparison with that of the control circuit based on a typically sequential circuit in the conventional FPGA and the fine-grain field-programmable VLSI reported until now.

Highly Reliable Multiple-Valued Current-Mode Comparator Based on Active-Load Dual-Rail Operation

In this paper, a multiple-valued current-mode (MVCM) circuit based on active-load dual-rail differential logic is proposed for a high-performance arithmetic VLSI system with crosstalk-noise immunity. The use of dual-rail complementary differential-pair circuits (DPCs), whose outputs are summed up by wiring makes it possible to reduce the common-mode noise, and yet enhance the switching speed. By using the diode-connected cross-coupled PMOS active loads, the rapid transition of switching in the DPC is relaxed appropriately, which can also eliminate spiked input noise. It is demonstrated that the noise reduction ratio and the switching delay of the proposed MVCM circuit in a 90nm CMOS technology is superior to those of the corresponding ordinary implementation.

Optimal design of a current-mode deep-submicron multiple-valued integrated circuit and application

This paper presents an optimal design method of a multiple-valued current-mode (MVCM) integrated circuit based on dual-rail source-coupled logic, in which both power dissipation and switching delay are minimized simultaneously. The minimum delay of the MVCM circuit is determined by the optimal gate-width ratio of MOS transistors in a current mirror and a threshold detector, which are connected serially. The gate width of all of the threshold detectors is minimized while keeping the above gate-width ratio, which minimizes power dissipation. As a typical example of the MVCM logic circuit, the performance of an optimized 54 × 54-bit multiplier is estimated to be about 1.7 times faster than that of a corresponding binary device under a standard 0.5-μm CMOS process technology with a supply voltage of 1.5 V. © 1998 Scripta Technica, Syst Comp Jpn, 29(11): 40–47, 1998

Comments on "High-speed area-efficient multiplier design using multiple-valued current-mode circuits"

S. Kawahito et al. (1988) presented multiplier designs using the binary-tree reduction feature of certain highly redundant radix-2 representations, along with multiple-valued current-mode circuit techniques, and shown them to compare favorably to those based on less redundant binary signed-digit and carry-save numbers. We point out that these representation schemes, and their potential advantages, have been discussed in earlier publications and that a more general view of the parallel-carries addition process exploited in these multipliers leads to other potentially useful representations. The authors reply is also given.

Design and evaluation of a multiple-valued arithmetic integrated circuit based on differential logic

A design of a new multiple-valued current-mode circuit for high-speed arithmetic systems is presented. The use of a differential logic circuit with dual-rail complementary inputs makes a signal-voltage swing small with a constant driving current, so that the delay of the circuit can be reduced. As an application to arithmetic systems, it is demonstrated that the operating speed of the radix-2 signed-digit (SD) adder based on multiple-valued current-mode differential logic is 1.3 times faster than that of the corresponding binary CMOS implementation at a 3.5 V supply voltage.

High-speed area-efficient multiplier design using multiple-valued current-mode circuits

Presents a very-large-scale-integration (VLSI)-oriented high-speed multiplier design method based on carry-propagation-free addition trees and a circuit technique, so-called multiple-valued current-mode (MVCM) circuits. The carry-propagation-free addition method uses a redundant digit set such as /spl lcub/0,1,2,3/spl rcub/ and /spl lcub/0,1,2,3,4/spl rcub/. The number representations using such redundant digit sets are called redundant positive-digit number representations. The carry-propagation-free addition is written by three steps, and the adder can be designed directly and efficiently from the algorithm using MVCM circuits. The designed multiplier internally using the MVCM parallel adder with the digit set /spl lcub/0,1,2,3/spl rcub/ in radix 2 has attractive features on speed, regularity of the structure, and reduced complexities of active elements and interconnections. A prototype CMOS integrated circuit of the MVCM parallel adder has been implemented, and its stable operation has been confirmed. Other possible schemes of multipliers with redundant digit sets using MVCM technology are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 32*32-bit multiplier using multiple-valued MOS current-mode circuits

A 32*32-bit multiplier using multiple-valued current-mode circuits has been fabricated in 2- mu m CMOS technology. For the multiplier based on the radix-4 signed-digit number system, 32*32-bit two's complement multiplication can be performed with only three-stage signed-digit full adders using a binary-tree addition scheme. The chip contains about 23600 transistors and the effective multiplier size is about 3.2*5.2 mm/sup 2/, which is half that of the corresponding binary CMOS multiplier. The multiply time is less than 59 ns. The performance is considered comparable to that of the fastest binary multiplier reported. >