Multiple Test Sets Research Articles

Multiple fault detection in two-level multi-output circuits

It is often stated that in irredundant two-level logic circuits, a test set for all single stuck faults will also detect all multiple stuck faults. We show by a simple example that this result does not hold for multi-output circuits even when each output function is prime and irredundant. Using a result from the programmable logic array technology, we give an output ordering constraint that, if satisfied during test generation, will make a single stuck fault test set a valid multiple stuck fault test set for irredundant two-level multi-output circuits.

Detection of multiple faults in MOS circuits

Test sets that detect multiple faults in MOS circuits are characterized, guided by the observation that such circuits are implemented as networks of switches. This leads to a conceptually simple technique for generating multiple fault test sets. Sufficient conditions for the detection of all multiple faults are given for switch networks, and it is shown that a test set exists meeting these conditions for any irredundant circuit with certain restrictions on fan out. In the cases where these conditions cannot be met, a class of robust test sets is presented. Test sets that generate complete multiple fault test sets with fewer vectors for many MOS complex gates than is possible using a gate-level description of the circuit are presented. >

Testing for multiple faults in domino-CMOS logic circuits

The problem of multiple faults detection in domino-CMOS logic circuits is considered. The multiple faults can be of the stuck-open and stuck-on types. It is shown that a multiple fault in the domino-CMOS circuit can be mapped to a multiple stuck-at fault in its gate-level model. A method is given to initialize the domino-CMOS circuit and apply a multiple stuck-at fault test set based on the gate-level model of the circuit. This results in the detection of all multiple faults having detectable consistent faults. The problem of test set invalidation due to arbitrary signal delays is easily taken care of in domino-CMOS circuits, making such an implementation of a function even more attractive than a fully complementary CMOS implementation, from the testability point of view. >

An efficient algorithm for single and multiple fault test sets generation

A direct approach for single and multiple fault test set generation on any number of lines of a logical circuit has been described in this paper. The present paper simplifies the results of Ku and Masson [2] for which only some visual inspections are needed rather than going through tedious steps of algebraic manipulations. This method is thus easily applicable to arbitrarily large combinational circuits, whether it is fan-out free or with fan-out nodes.

A Remark on the Nonminimality of Certain Multiple Fault Detection Algorithms

Poage has constructed a complex fault detection algorithm which generates a complete and minimal test set of all multiple stuck-at faults of a given combinational network. Several authors have derived from his method fast and simple multiple fault detection algorithms, which are claimed to generate complete test sets with a near-minimal or near-optimal number of tests. We show that the algorithms by Bossen and Hong and the algorithm by Yang and Yau may generate test sets with an exponential number of tests (relative to the number of inputs) where a linear number of tests is sufficient for a complete multiple fault detection test set.

An algorithm for multiple fault detection in combinational logic networks

A simple algorithm for finding multiple fault test sets in combinational logic networks is presented. The method is based on finding boolean differences and hence test sets using augmented boolean matrices. An example is given which illustrates the procedure.

Minimal Fault Tests for Combinational Networks

The problem of how to determine minimal sets of tests for single and multiple faults in irredundant combinational circuits is dealt with. It is shown that the Equivalent Sum of Products form of the given network contains all the information necessary to derive a min; mal test set. A simple procedure which generates a minimal test set Ts for single faults is described. Fault masking is then studied and it is shown how to find the multiple faults undetected by Ts. Finally a method which derives a nearly minimal multiple fault test set Tm where Ts [mi][/mi] Tm is given.

Two Types of Waveguide Switches

In the design of Century Electronics' multiple function test set, the problem of waveguide switching between the various functions arose. The problem could have been solved by using sheer force, but space, weight, and economic requirements ruled out this approach. A study was accordingly made to see if new techniques could be used, and from this study two useful types of switches evolved.