Multiple Scan Paths Research Articles

ASIC Implementation for Multiple Scan at Register Transfer Level

Design for testability (DFT) is introduced to reduce the complexity of testing integrated circuit and help improve fault coverage. However, conventional DFT with additional 2-to-1 multiplexer (MUX) might add an increasing amount of delay and area overhead. Therefore, register transfer level (RTL) scan design is introduced to overcome this problem. This paper aims to present the development of an ASIC with RTL scan design by using multiple scan paths instead of the conventional technique, which is gate-level (GL) scan insertion to insert scan cells. This method inserts multiple scan cells by utilizing the existing multiplexer and operational units in order to reduce area overhead and delay. Besides, multiple scan paths are implemented instead of a single scan chain to reduce the complexity of the testing process, where a single scan chain has long test application times due to the high number of clock cycles for the scan chain process. RTL design is also modified by adding an extra gate for multiple scan chain insertion. The graph is derived in order to analyse the connection between registers such that the multiple scan paths can be determined accordingly. Synopsys tool is used for synthesized, placement and routing and performing automatic test pattern generation while static timing analysis is used to verify the results of the setup slack time for ASIC design. The simulation result shows that multiple scan paths insertion at RTL level has an area overhead and slack time of about 3.79% and 0.44ns less compared to multiple scan paths insertion at GL for a finite impulse response circuit with comparable high fault coverage and small delay. A comparison of the performance metrics such as area, setup slack time, and fault coverage of the multiple scan chain is done between the RTL scan and GL scan.

Visual Scan-Path based Data-Augmentation for CNN-based 360-degree Image Quality Assessment

360-degree Image quality assessment (IQA) is facing the major challenge of lack of ground-truth databases. This problem is accentuated for deep learning based approaches where the performances are as good as the available data. In this context, only two databases are used to train and validate deep learning-based IQA models. To compensate this lack, a dataaugmentation technique is investigated in this paper. We use visual scan-path to increase the learning examples from existing training data. Multiple scan-paths are predicted to account for the diversity of human observers. These scan-paths are then used to select viewports from the spherical representation. The results of the data-augmentation training scheme showed an improvement over not using it. We also try to answer the question of using the MOS obtained for the 360-degree image as the quality anchor for the whole set of extracted viewports in comparison to 2D blind quality metrics. The comparison showed the superiority of using the MOS when adopting a patch-based learning.

Representative Scanpath Identification for Group Viewing Pattern Analysis.

Scanpaths are composed of fixations and saccades. Viewing trends reflected by scanpaths play an important role in scientific studies like saccadic model evaluation and real-life applications like artistic design. Several scanpath synthesis methods have been proposed to obtain a scanpath that is representative of the group viewing trend. But most of them either target a specific category of viewing materials like webpages or leave out some useful information like gaze duration. Our previous work defined the representative scanpath as the barycenter of a group of scanpaths, which actually shows the averaged shape of multiple scanpaths. In this paper, we extend our previous framework to take gaze duration into account, obtaining representative scanpaths that describe not only attention distribution and shift but also attention span. The extended framework consists of three steps: Eye-gaze data preprocessing, scanpath aggregation and gaze duration analysis. Experiments demonstrate that the framework can well serve the purpose of mining viewing patterns and “barycenter” based representative scanpaths can better characterize the pattern.

Identifying Aggregate Scanning Strategies to Improve Usability Evaluations

Automated analysis methods are needed to convert eye tracking data into meaningful descriptions of high-level scanning strategies that can help usability professionals understand how designs are viewed. Prior techniques for analyzing eye tracking sequences, or scanpaths, are limited in their ability to find aggregated visual search strategies for a group of observers. We describe a pattern analysis tool that finds clusters of sequentially matching patterns among multiple scanpaths. Scanning strategies are clustered hierarchically, then represented as aggregate scanpaths. The tool can also match scanpaths against a hypothetical scanning strategy, input by mouse gesture. Use of the pattern analysis tool was demonstrated using a 114-participant eye tracking dataset in which several aggregate scanning strategies were identified. Matching against a hypothetical, counter-clockwise scanning strategy was also included in the demonstration. The analysis tool provides a valuable resource for aggregating or grouping scanning strategies, a vital step toward generalizing eye tracking results to guide design recommendations for improving usability.

E-BIST: enhanced test-per-clock BIST architecture

A new built-in self-test architecture, E-BIST, suitable for a test-per-clock scheme, is proposed. The E-BIST architecture is based on STUMPS, which uses a linear feedback shift register (LFSR) as the test generator, a multiple input shift register (MISR) as the response compactor, and shift register latch (SRL) channels as multiple scan paths. In E-BIST a degenerate MISR structure is used for every SRL channel; this offers reduced area overheads and has less impact on performance than the STUMPS technique. It is also shown that the masking probability of the proposed SRL channel structure is 21−(N+L), where N and L are the number of test patterns and the length of the SRL channel, respectively. Results of the experiments on ISCAS 89 benchmark circuits show that this architecture is also suitable for robustly detecting path delay faults, with improved fault coverage, when the Hamming distance of the data in the SRL channel is considered.

Deterministic BIST with Multiple Scan Chains

A deterministic BIST scheme for circuits with multiple scan paths is presented. A procedure is described for synthesizing a pattern generator which stimulates all scan chains simultaneously and guarantees complete fault coverage. The new scheme may require less chip area than a classical LFSR-based approach while better or even complete fault coverage is obtained at the same time.