Multiple Processor Systems Research Articles

RADARS, a bioinformatics solution that automates proteome mass spectral analysis, optimises protein identification, and archives data in a relational database

RADARS, a rapid, automated, data archiving and retrieval software system for high-throughput proteomic mass spectral data processing and storage, is described. The majority of mass spectrometer data files are compatible with RADARS, for consistent processing. The system automatically takes unprocessed data files, identifies proteins via in silico database searching, then stores the processed data and search results in a relational database suitable for customized reporting. The system is robust, used in 24/7 operation, accessible to multiple users of an intranet through a web browser, may be monitored by Virtual Private Network, and is secure. RADARS is scalable for use on one or many computers, and is suited to multiple processor systems. It can incorporate any local database in FASTA format, and can search protein and DNA databases online. A key feature is a suite of visualisation tools (many available gratis), allowing facile manipulation of spectra, by hand annotation, reanalysis, and access to all procedures. We also described the use of Sonar MS/MS, a novel, rapid search engine requiring 40 MB RAM per process for searches against a genomic or EST database translated in all six reading frames. RADARS reduces the cost of analysis by its efficient algorithms: Sonar MS/MS can identifiy proteins without accurate knowledge of the parent ion mass and without protein tags. Statistical scoring methods provide close-to-expert accuracy and brings robust data analysis to the non-expert user.

Program analysis techniques for transforming programs for parallel execution

In a multiple processor system, computer programs have to be redesigned to efficiently use the parallel processors and deliver higher performance. One major approach is automatic detection of parallelism, in which existing conventional sequential programs are translated into parallel programs, in order to benefit from the presence of multiple processors. Optimizing compilers rely upon program analysis techniques to detect data dependences between program statements. The results of the analysis enable the compiler to identify code fragments that can be executed in parallel. The proposed dependence analysis techniques fall into two different categories: either efficient and approximate tests or exact but exponential. In this paper, we show that exact data dependence information can be computed efficiently in practice. The Banerjee inequality and the GCD test are the two tests traditionally used to determine statement data dependence in automatic parallelization of loops. These tests are approximate in the sense that they are necessary but not sufficient conditions for data dependence. In an earlier work we formally studied the accuracy of the Banerjee and GCD tests and derived a set of conditions that can be tested along with the Banerjee inequality and the GCD test to obtain exact data dependence information. In this work, we perform an empirical study to explain and demonstrate the accuracy of the Banerjee and GCD tests in actual practice. Our experiments indicate that exact data dependence information can be computed in linear time in practice.

Optimal scheduling of tracing computations for real-time vascular landmark extraction from retinal fundus images.

Recently, this group published fast algorithms for automatic tracing (vectorization) of the vasculature in live retinal angiograms, and for the extraction of visual landmarks formed by vascular bifurcations and crossings. These landmarks are used for feature-based image matching for controlling a computer-assisted laser retinal surgery instrument currently under development. This paper describes methods to schedule the vascular tracing computations to maximize the rate of growth of quality of the partial tracing results within a frame cycle. There are two main advantages. First, progressive image matching from partially extracted landmark sets can be faster, and provide an earlier indication of matching failure. Second, the likelihood of successful image matching is greatly improved since the extracted landmarks are of the highest quality for the given computational budget. The scheduling method is based on quantitative measures for the computational work and the quality of landmarks. A coarse grid-based analysis of the image is used to generate seed points for the tracing computations, along with estimates of local edge strengths, orientations, and vessel thickness. These estimates are used to define criteria for real-time preemptive scheduling of the tracing computations. It is shown that the optimal schedule can only be achieved in perfect hindsight, and is thus unrealizable. This leads to scheduling heuristics that approximate the behavior of the optimal algorithm. One such approximation produced approximately 400% improvement in the quality of the partial results at a defined milestone, as compared to random scheduling. The resulting algorithm can be readily implemented on conventional and multiple-processor systems, and is being applied to computer-assisted laser retinal surgery.

Optoelectronic parallel-matching architecture: architecture description, performance estimation, and prototype demonstration

We propose an optoelectronic parallel-matching architecture (PMA) that provides powerful processing capabilities in global processing compared with conventional parallel-computing architectures. The PMA is composed of a global processor called a parallel-matching (PM) module and multiple processing elements (PE's). The PM module is implemented by a large-fan-out free-space optical interconnection and a PM smart-pixel array (PM-SPA). In the proposed architecture, by means of the PM module each PE can monitor the other PE's by use of several kinds of global data matching as well as interprocessor communication. Theoretical evaluation of the performance shows that the proposed PMA provides tremendous improvement in global processing. A prototype demonstrator of the PM module is constructed on the basis of state-of-the-art optoelectronic devices and a diffractive optical element. The prototype is assumed for use in a multiple-processor system composed of 4 x 4 PE's that are completely connected through bit-serial optical communication channels. The PM-SPA is emulated by a complex programmable device and a complementary metal-oxide semiconductor photodetector array. On the prototype demonstrator the fundamental operations of the PM module were verified at 15 MHz.

Efficient approaches for constructing a massively parallel processing system

Abstract How to construct a massively parallel processing system has drawn a lot of attention. An important feature affecting the performance and characteristics of the architecture with an interconnection of multiple processors is its configuration design and scalability of the system. Good performance of a parallel application is often the result of an appropriate match between the processes of the parallel application and the configuration of multiple processor system. In order to accommodate different parallel applications, it is highly desirable that the configuration of the architecture and the number of processors can be modified easily and extended flexibly. Two efficient technical approaches for constructing a massively parallel processing system with scalability are proposed. One is based on multilayered motherboards and the other on crossbar switches. The technique and the two approaches have been adapted in a real-life application which is a parallel implementation of backpropagation neural computation. Performance evaluation for the two approaches is included.

Efficient Block Scheduling to Minimize Context Switching Time for Programmable Embedded Processors

Scheduling is one of the most often addressed optimization problems in DSP compilation, behavioral synthesis, and system-level synthesis research. With the rapid pace of changes in modern DSP applications requirements and implementation technologies, however, new types of scheduling challenges arise. This paper is concerned with the problem of scheduling blocks of computations in order to optimize the efficiency of their execution on programmable embedded systems under a realistic timing model of their processors. We describe an effective scheme for scheduling the blocks of any computation on a given system architecture and with a specified algorithm implementing each block. We also present algorithmic techniques for performing optimal block scheduling simultaneously with optimal architecture and algorithm selection. Our techniques address the block scheduling problem for both single- and multiple-processor system platforms and for a variety of optimization objectives including throughput, cost, and power dissipation. We demonstrate the practical effectiveness of our techniques on numerous designs and synthetic examples.

Future developments in nuclear medicine instrumentation: a review.

This review article forecasts developments in nuclear medicine instrumentation which are on the horizon. Special attention is paid to the physical properties of detectors and multiple-processor parallel processing systems needed for fast and high-quality imaging in emission tomography. Advances in detector technology will improve imaging resolution below 5 mm and will increase sensitivity and quantitative accuracy. In addition, high count rate list-mode acquisition enables 'true' four-dimensional data-sets. A sandwich-like construction of two different crystals allows the simultaneous use of conventional tracers and positron tracers (multiple emission tomography, MET). Transmission-based attenuation and scatter compensation with fast iterative reconstruction methods will further improve image quality. The clinical and scientific importance of improved images and the limits on advances in instrumentation are also reviewed.

LSTF: A new scheduling policy for complex real-time tasks in multiple processor systems

We propose a new algorithm, least space-time first (LSTF), for dealing with the general complex-taskmultiple-processor model. The results of the proof and simulation shown that LSTF outperforms other established heuristic algorithms (such as earliest-deadline-first) in the sense that it minimizes the maximum tardiness of a set of tasks. LSTF can gracefully incorporate some realistic overhead assumptions, such as context switch.

A memory interference model for regularly patterned multiple stream vector accesses

Most existing analytical models for memory interference generally assume random bank selection for each memory access. In vector computers, however, memory accesses are typically regularly patterned with a number of data items being accessed concurrently from different banks. Very little is known about the queueing behavior of memory interferences in multiple stream vector accesses. This paper presents an analytical model for memory interferences due to vector accesses in multiple vector processor systems. The model captures the effects of both bank conflicts among elements within one vector access stream and conflicts among multiple vector access streams on system performance. The model is based on a closed queueing network assuming an ideal interconnection network. An approximation technique is proposed to solve the memory queueing system that serves customers in a complicated way (non-FIFO). We also carry out extensive simulation experiments to study memory interference and validate our analytical model. Simulation results and analytical results are in a very good agreement, indicating that the model is very accurate. We further validate our analysis by comparing the numerical results obtained from our analytical model with those measurement results that were published by other researchers. Based on our analytical model and simulations, we carry out performance evaluation of the multiple vector processor systems. Our numerical results show that memory access conflicts pose a severe limitation on the number of useful processors in the system, implying that memory system design is essential to high-performance computing. >

A comparison of interconnection methods for multi-robot systems

To analyze a multiple-robot system, several interconnection methods are presented in terms of the processor-based architecture. The concepts of the multiple-processor system, and the multiple-computer system are used to formulate and analyze the multi-robot interconnection system (MRIS). A comparative performance study is presented for four kinds of models of the MRIS. Performance evaluation is then achieved for the MRIS through queueing analysis and Petri net models, especially for the response time and the probability of service failure under different workloads. To verify the significance of the proposed analytic method, a computer simulation is carried out with some design issues for the MRIS. The results, together with some comments, suggest a useful guideline for selecting an appropriate interconnection method for multi-robot systems, subject to the system environment and application.

A comparative model-based analysis and design for multi-robot systems

SummaryFor a robotic workcell with multiple robots, several interconnection methods are presented in terms of a processor-based architecture. The concept of the multiple processor system (MPS) or multiple computer system (MCS) is used to formulate and analyze the multi-robot interconnection system (MRIS). The MRIS is modelled as a queueing network, and mathematical analysis is done on the basis of modelling. Performance evaluation is achieved for the MRIS through the mean value analysis with the response time and the probability of service failure under different workloads. The results together with some comments suggest a useful guideline for a selecting an appropriate interconnection method for the MRIS subject to the system environment and application.

Least-Space-Time-First Scheduling Algorithm: A Policy for Complex Real-Time Tasks in Multiple Processor Systems

Significant prior work exists on scheduling for the ’simple-tasks-single-processor’, ’simple-tasks-multiple-processor’, and ’complex-tasks-single-processor’, but few researchers have yet considered the ’complex-tasks-multiple-processor’ model. We propose a new algorithm, Least Space-Time First (LSTF), to deal with the general ’complex-task-multiple-processor’ model. We demonstrate that LSTF outperforms the Highest-Level-First, Earliest Deadline-First and Least-Laxity-First scheduling disciplines in the sense of minimizing maximum tardiness of a set of tasks. LSTF can gracefully incorporate some realistic overhead assumptions, including context switch and communication. The Unit Precedence Graph and Soft-Precedence Edges significantly facilitate implementation of LSTF.

An algorithm for optimal load balancing in a multiple GI/G/1 queueing system

AbstractThe issue of optimal load balancing has been raised in several important engineering fields such as the file management in a data base, the job control in a multiple processor system or the flow assignment in a packet switched data network. By modeling the subsystems as multiple GI/G/1 queues and applying known approximations and decomposition methods, the system mean response time is expressed as a function of the load allocation. To find the optimal load balancing, the convexity property is first studied with respect to the type of the arrival process of the system. We give then an efficient algorithm which finds for the convex case the global and for the non‐convex case a local minimum. Some important properties of the multiple Gl/G/1 queueing system are revealed with several numerical examples.

Least-space-time-first scheduling algorithm: A policy for complex real-time tasks in multiple processor systems

Significant prior work exists on scheduling for the ‘simple-tasks-single-processor’, ‘simple-tasks-multiple-processor’, and ‘complex-tasks-single-processor’, but few researchers have yet considered the ‘complex-tasks-multiple-processor’ model. We propose a new algorithm, Least Space-Time First (LSTF), to deal with the general ‘complex-task-multiple-processor’ model. We demonstrate that LSTF outperforms the Highest-Level-First, Earliest-Deadline-First and Least-Laxity-First scheduling disciplines in the sense of minimizing maximum tardiness of a set of tasks. LSTF can gracefully incorporate some realistic overhead assumptions, including context switch and communication. The Unit Precedence Graph and Soft-Precedence Edges significantly facilitate implementation of LSTF.

A General Framework for the Design of Multiple Processor Controllers

This paper discusses various problems involved in the design of multiple processor systems for process control applications. Topics covered include: software and hardware architectures of computing systems for control applications, the design of multiple processor control systems related to the algorithm used and to the implementation problems, examples of multiple processor systems. The aims of the paper are, firstly, to provide a general framework for the analysis and comparison of different architectural solutions and, secondly, to present a project methodology.

Computation of transients by parallel processing

Transients are computed on a multiple instruction/multiple data (MIMD) parallel processor system. Several communicating processes are generated by splitting the lines of a network. The implementation on a real multiple processor system is described. Problems are elaborated and one possible solution is suggested. Specific examples achieved on a network of 8 transputers are discussed. The relation between the structure of a network and its potential speedup with this method is discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Computing the future: a broader agenda for computer science and engineering

Computers are increasingly the enabling devices of the information revolution, and computing is becoming ubiquitous in every corner of society, from manufacturing to telecommunications to pharmaceuticals to entertainment. Even more importantly, the face of computing is changing rapidly, as even traditional rivals such as IBM and Apple Computer begin to cooperate and new modes of computing are developed. Computing the Future presents a timely assessment of academic computer science and engineering (CS&E), examining what should be done to ensure continuing progress in making discoveries that will carry computing into the twenty-first century. Most importantly, it advocates a broader research and educational agenda that builds on the field's impressive accomplishments. The volume outlines a framework of priorities for CS&E, along with detailed recommendations for education, funding, and leadership. A core research agenda is outlined for these areas: processors and multiple-processor systems, data communications and networking, software engineering, information storage and retrieval, reliability, and user interfaces. This highly readable volume examines * Computer science and engineering as a discipline--how computer scientists and engineers are pushing back the frontiers of their field. * How CS&E must change to meet the challenges of the future. * The influence of strategic investment by federal agencies in CS&E research. * Recent structural changes that affect the interaction of academic CS&E and the business environment. * Specific examples of interdisciplinary and applications research in four areas: earth sciences and the environment, computational biology, commercial computing, and the long-term goal of a national electronic library. The volume provides a detailed look at undergraduate CS&E education, highlighting the limitations of four-year programs, and discusses the emerging importance of a master's degree in CS&E and the prospects for broadening the scope of the Ph.D. It also includes a brief look at continuing education.

Concept of a crossbar switch for large-scale multiple processor systems in the field of process control

Large-scale multiple processor systems are already widely used in the field of process control. They are real-time systems and differ considerably from traditional computer systems. Such systems are used to perform a large variety of relatively complex tasks, many of them extremely time-critical. In the near future, the tasks will increase in number and size and will become even more time-critical, caused, for instance, by the expected integration of expert systems in process control. The question naturally arises as to whether or not such an increase of the requirements could be met by a straightforward enhancement of present designs [10], the interconnection network being in any case the key issue. The paper describes the concept of a new crossbar switch design, based on the use of so-called configurational processors that would be extraordinarily well suited to the specific requirements in the field of process control. The new design principle is VLSI-compatible; the whole crossbar switch can be implemented with building blocks of one type. It is possible to arrange these components for the crossbar switch in close proximity to the processing elements, which are physically distributed throughout the whole area of a plant. This characteristic, in combination with the use of bitserial buses, allows a crossbar switch to be implemented in an advantageous manner, particularly without excessive cabling costs.

Selection criteria in the development of a multiple processor based DSP system

This paper notes the selection criteria and the hardware/software alternatives for the construction of a multiple processor system dedicated to handling digital signal processing (DSP) applications, primarily for the analysis of speech signals. The paper initially presents brief descriptions of the different architectural options available for a multiple DSP system. A list of the criteria to be used in the selection of the type of DSP system is detailed and the criteria are then used to aid in the selection of the architecture. From the criteria it is concluded that the use of a loosely coupled transputer based system allows the maximum flexibility for such a system. To aid in the real-time operation of the system it is further proposed to incorporate a front-end data processing mechanism based on the combination of a transputer and a floating-point DSP processor.

An efficient algorithm for a task allocation problem

This paper presents an efficient algorithm to solve one of the task allocation problems. Task assignment in an heterogeneous multiple processors system is investigated. The cost function is formulated in order to measure the intertask communication and processing costs in an uncapacited network. A formulation of the problem in terms of the minimization of a submodular quadratic pseudo-Boolean function with assignment constraints is then presented. The use of a branch-and-bound algorithm using a Lagrangean relaxation of these constraints is proposed. The lower bound is the value of an approximate solution to the Lagrangean dual problem. A zero-duality gap, that is, a saddle point, is characterized by checking the consistency of a pseudo-Boolean equation. A solution is found for large-scale problems (e.g., 20 processors, 50 tasks, and 200 task communications or 10 processors, 100 tasks, and 300 task communications). Excellent experimental results were obtained which are due to the weak frequency of a duality gap and the efficient characterization of the zero-gap (for practical purposes, this is achieved in linear time). Moreover, from the saddle point, it is possible to derive the optimal task assignment.