Multiple Power Modes Research Articles

Tunable, Asynchronous, and Nanopower Baseband Receiver for Charging and Wakeup of IoT Devices

This article proposes a novel ultra-low power, tunable, and asynchronous baseband architecture for joint radio-frequency (RF) wakeup and charging receivers. The designed system switches between the wakeup and charging operations based on the type of the received RF signal. To our knowledge, the proposed system is the first of a kind that introduces multiple power states to reduce the energy consumption by sequentially activating minimal components required for RF wakeup or charging. The fabricated prototype, using off-the-shelf components, features a sensitivity of −40 dBm, a bit rate of 500 bps, and a current consumption of 225 nA at a bias voltage of 2.6 V in the listening state. Current consumption is estimated at 3.225 and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$13.725~\mu \text{A}$ </tex-math></inline-formula> while processing the preamble and bit sequence, respectively. The address detector is powered OFF during charging to reduce the system’s current consumption to 150 nA. Our experimental results show that shutting down the address detector during charging reduces charging time and allows charging from received power levels that are as low as −6 dBm. We demonstrate that operating the detector with multiple power modes reduces its current consumption and enhances its noise immunity when compared to conventional address detectors with two power modes of operation.

Design of the Water-Cooled Ceramic Breeder blanket for CFETR

The Water-Cooled Ceramic Breeder (WCCB) blanket is one of the blanket candidates for the Chinese Fusion Engineering Testing Reactor (CFETR). In the current version, the WCCB blanket was designed to fulfill the requirements of operating in multiple fusion power modes (200 MW, 500 MW, 1 GW and 1.5 GW) of CFETR while satisfying the tritium self-sufficiency. Structural designs were carried out for typical inboard and outboard modules. Adequate neutron shielding capability and acceptable thermo-mechanical performance were achieved according to the analyses. The global Tritium Breeding Ratio (TBR) was 1.165 with full blanket coverage. It reduced to 1.052 considering the ports occupied by auxiliary heating systems and diagnostic systems. Eventually, the TBR increased to 1.123 by applying the approach of divertor blanket. Besides, two independent cooling systems were applied to adapt to different fusion powers. One cooling system provided coolant for the first wall, the other for breeder zones. The corresponding Primary Heat Transfer System (PHTS) was designed and main operation parameters were obtained under the fusion power of 200 MW∼1.5 GW.

Smart Power Unit—mW-to-nW Power Management and Control for Self-Sustainable IoT Devices

Self-sustainability and intelligence will be critical features of the next generation of Internet of Things devices. Power management circuits need to be energy-efficient in multiple power modes, from nW sleep to mW active, and to support energy harvesting (EH) from multiple environmental sources. This article presents an adaptive and firmware-configurable power supply unit that enables intelligent devices to operate in the sub μW range while achieving self-sustainability through EH. The microcontroller-based design allows efficient conversion from batteries, dc, ac environmental sources, and nA quiescent currents. Source and load power points are decoupled with multiple dc–dc converters aiming to supply loads with adaptive voltage scaling and achieving high reliability. Experimental results show the flexibility and efficiency of this approach: the proposed power supply unit achieves a quiescent current of 54 nA and a maximum peak load current of 300 mA, delivered with an end-to-end power efficiency above 85%.

Power-aware throughput control for containerized relational operation

As the high performance computing (HPC) moves towards AI-driven applications, these AIHPC applications demand steady and high-throughput relational data acquisition from data sites, which gradually dominates the whole computing process. In order to provide an energy-efficient service in a multi-tenant environment, we have to reduce the power consumption from serving relational data, such that the energy cost can be best amortized. While modern hardware provide multiple power modes, these power performance tradeoffs cannot be directly applied to data services due to the lack of understanding from the operation behavior under different power modes. To address this challenge, we provide an system identification study on learning the power behavior under serving database operations under different hardware modes, and propose a Control framework for Relational Operations to save Power. In contrast to today’s heuristic-based power tuning techniques, our solution achieves the goal via two facilities: (1) a control-theory based controller design that minimizes overshoot and guarantees the minimum settling time, thus control accuracy and system stability; (2) a fuzzy classifier inside database engine that helps to understand software behavior, in order to tune the sensitivity of the whole system control. We prototyped Crop as wrapping these functions in a container hierarchy, and evaluate it with workloads generated from various database benchmarks. The results show that Crop achieves up to 51.3% additional energy savings despite runtime workload dynamics and model errors, as compared to other competing methods.

Power management of multi-source network hydraulic system with multiple actuators

The mismatch between the load and pump sources and the restriction of energy recovery lead to large energy losses and lower energy efficiency in high power multi-actuator hydraulic systems. To obtain high energy efficiency, this paper develops a Multi-Source Network Hydraulic System (MSNHS) with multiple actuators and a corresponding power management strategy (PMS) to reduce the throttling losses and recover energy. The multiple energy-saving power modes based on the path of power transmissions, composed of different combinations of six power units with energy conversion and transfer, are implemented on MSNHS to supply and regenerate or recover power for various load conditions. Thus, the power consumption models of each power unit are established to analyze the power consumption characteristics for itself and power modes. On this basis, the switching supervisory controller is proposed to select an optimal mode for the current condition by utilizing an objective optimized function of minimal power consumption. Besides, the switching rules among power modes are designed, and the logical threshold control is presented for the multi-mode switching under different working conditions. The combination of the switching supervisory controller of optimal mode and the logical threshold control realizes the power management of the MSNHS with multiple actuators to accommodate with time-varying load and recover potential energy. The experimental validation is conducted on the MSNHS platform by simulating a 90° truck-loading cycle of the excavator. Experimental results demonstrate that the PMS applied to the MSNHS can downsize engine input power by up to 60.27% compared with the theoretical calculation of conventional one, and then improve overall system energy efficiency.

Multi-mode nanoFETs: From low power to high performance on demand

Dynamic power management at the lowest design level of electronic hardware, i.e. at the device or transistor level, is still a novelty. Instead, energy saving is usually achieved at the circuit level by switching off high performance components and activating low leakage transistors in the current paths. We discuss here performance projections of field-effect transistors providing multiple power modes. A multi-mode (mm) FET can be configured from GHz performance to ultralow leakage by adjusting the charge injection into the transistor channel between thermionic and band-to-band tunnel injection. Nanodevices with ultrathin doping-free channels are the enabler of this novel device concept that requires excellent electrostatic control of the charge type and density. Moreover, nanomaterials with charge carriers of low effective mass will improve the mode tuning of mmFETs. TCAD simulations show that the device current can be switched through nine orders of magnitude at a supply voltage of . The mmFET can also operate in a low dynamic power mode with reduced drive currents but delay times that still allow sub-MHz operation. These properties make mmFETs a promising technology for low power circuitry supplied only by energy harvesters. The possibility to further decrease the supply voltage by integrating a ferroelectric layer in the capacitor stack is also addressed.

A Scenario-Based Stochastic Optimization Approach for Non-Intrusive Appliance Load Monitoring

In this paper an energy disaggregation problem, commonly studied as “non-intrusive load monitoring”, is presented. Non-intrusive load monitoring is a procedure for estimating the energy profiles of individual electric home appliances from the aggregated power measurement. We present this problem as an optimization-based problem in which the least-square errors are minimized to find the set of active appliances, using the instantaneous aggregated power. The convex regularization terms are also added, which exploit the information of the probability of individual appliance usage and assume the behavior of the appliances’ power profiles to be constant as piecewise signal over time. The problem is formulated using a scenario-based stochastic optimization approach to consider the underlying uncertainties in power measurements. The expected value of the problem’s objective function is computed by using the sample average approximation method, where normally distributed samples of a random variable are introduced into the problem using the Monte Carlo simulation. Moreover, the appliances’ limits on the power modes are formulated as a chance constraint in the optimization problem. The training and testing of the proposed algorithm are done by using the benchmark data: AMPds and REFIT. The simulation results show that the proposed scenario-based stochastic optimization approach successfully estimates the energy profiles of individual appliances with multiple power modes.

Steady states and LOFA analyses of the updated WCCB blanket for multiple fusion power modes of CFETR

The Water Cooled Ceramic Breeder (WCCB) blanket is one of the blanket candidates of Chinese Fusion Engineering Test Reactor (CFETR). The core parameters of CFETR have been updated to major radius R = 7.2 m, minor radius a = 2.2 in 2018. Accordingly, the WCCB blanket design was also updated to satisfy multiple operation modes of CFETR with the fusion power of 200 MW, 500 MW, 1.0 GW and 1.5 GW. The WCCB blanket is characterized by 3 independent cooling systems (CSs), namely CS1 for the cooling of the First Wall (FW), CS2&3 for Breeding Zones (BZs). At 200 MW of low fusion power, CS3 is idle. At 500 MW to 1.5 GW of high fusion power, all 3 CSs are put into use to ensure adequate cooling. So it is indispensable to evaluate the feasibility of the updated WCCB blanket from the thermal hydraulic and safety point of view. A system analysis code RELAP5, was employed to model the blanket. The steady states were analyzed under 200 MW, 500 MW, 1.0 GW and 1.5 GW of fusion power. Then, the Loss of Flow Accident (LOFA) was simulated with different assumptions to verify the robustness of 3 cooling systems design under different initial postulations. Simulation results show that important thermal hydraulic parameters, such as pressure and temperature, can basically meet the design criterion, which preliminarily verifies the feasibility of the WCCB blanket from the thermal hydraulic safety point of view. Comprehensive system design and analysis is under way.

A Fully Integrated 2:1 Self-Oscillating Switched-Capacitor DC–DC Converter in 28 nm UTBB FD-SOI

The importance of energy-constrained processors continues to grow especially for ultra-portable sensor-based platforms for the Internet-of-Things (IoT). Processors for these IoT applications primarily operate at near-threshold (NT) voltages and have multiple power modes. Achieving high conversion efficiency within the DC–DC converter that supplies these processors is critical since energy consumption of the DC–DC/processor system is proportional to the DC–DC converter efficiency. The DC–DC converter must maintain high efficiency over a large load range generated from the multiple power modes of the processor. This paper presents a fully integrated step-down self-oscillating switched-capacitor DC–DC converter that is capable of meeting these challenges. The area of the converter is 0.0104 mm2 and is designed in 28 nm ultra-thin body and buried oxide fully-depleted SOI (UTBB FD-SOI). Back-gate biasing within FD-SOI is utilized to increase the load power range of the converter. With an input of 1 V and output of 460 mV, measurements of the converter show a minimum efficiency of 75% for 79 nW to 200 µW loads. Measurements with an off-chip NT processor load show efficiency up to 86%. The converter’s large load power range and high efficiency make it an excellent fit for energy-constrained processors.

Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modes

Meeting clock skew constraint is one of the most important tasks in the synthesis of clock trees. Moreover, the problem becomes much hard to tackle as the delay of clock signals varies dynamically during execution. Recently, it is shown that adjustable delay buffer (ADB) whose delay can be adjusted dynamically can solve the clock skew variation problem effectively. However, inserting ADBs requires non-negligible area and control overhead. Thus, all previous works have invariably aimed at minimizing the number of ADBs to be inserted, particularly under the environment of multiple power modes in which the operating voltage applied to some modules varies as the power mode changes. In this work, unlike the previous works which have solved the ADB minimization problem heuristically or locally optimally, we propose an elegant and easily adoptable solution to overcome the limitation of the previous works. Precisely, we propose an O(nlogn) time (bottom-up traversal) algorithm that (1) optimally solves the problem of minimizing the number of ADBs to be allocated with continuous delay of ADBs and (2) enables solving the ADB allocation problem with discrete delay of ADBs to be greatly simple and predictable. In addition, we propose (3) a systematic solution to an important extension to the problem of buffer sizing combined with the ADB allocation to further reduce the ADBs to be used. The experimental results on benchmark circuits show that compared to the results produced by the best known ADB allocation algorithm, our proposed algorithm uses, on average under 30–50ps clock skew bound, 13.5% and 15.8% fewer numbers of ADBs for continuous and discrete ADB delays, respectively. In addition, when buffer sizing is integrated, our algorithm uses 31.7% and 31.3% fewer numbers of ADBs, even reducing the area of ADBs and buffers by 15.0% and 16.3% for continuous and discrete ADB delays, respectively.

A Skew-Window based Methodology for Timing Fixing in Multiple Power Modes

In the low power design of integrated circuits, multiple power modes and clock gating are the two common techniques to reduce dynamic power consumption. In the multiple power modes designs, replacing some of the normal buffers with adjustable delay buffers (ADBs) and assign different delay values in different power modes is one of the promising solutions to satisfy the clock skew constraint. On the other hand, when the clock gating technique is applied, usually gate splitting is necessary to satisfy the enable timing constraint. However, both ADBs insertion and gate splitting increase the hardware cost. In this paper, under both the enable timing constraint and clock skew constraint, we propose a skew-window based methodology to reduce the total hardware cost of ADBs and clock gates simultaneously. In comparison with when only ADBs insertion or gate splitting technique is applied, experimental results show that our methodology can satisfy the constraints in all the power modes and reduce the hardware cost effectively.

A Low RF-Band Impedance Spectroscopy Based Sensor for In Situ, Wireless Soil Sensing

A novel on-board solution for a robust, accurate and self-calibrating soil moisture and nutrient sensor with inbuilt wireless transmission and reception capability is presented. The sensor can make real time and accurate measurement of subsurface soil moisture and nutrients and is ideally suited to act as a node in a network spread over a large area. It works on the principle of impedance spectroscopy. Impedance measurement at multiple frequencies is done by comparing the amplitude and phase of signals incident on and reflected from the soil in proximity of the sensor. A distributed transmission line model for the on-board connections is employed to improve the accuracy of measurements. Variations in temperature and surroundings are accounted by realizing a built-in self-calibrating mechanism which operates on the standard short-open-load technique. This also accounts for the parasitic impedance of the board in the measurements to minimize the errors. Measurements of both real and imaginary parts of soil impedance at multiple frequencies give the sensor an ability to detect variations in ionic concentrations other than soil moisture content. A switch-controlled multiple power mode transmission and reception is provided to support highly energy efficient medium access control.

A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital Systems

The clock buffer polarity assignment is one of the effective design schemes to mitigate the power/ground noise caused by the clock signal propagation in high-speed digital systems. This paper overcomes a set of fundamental limitations of the conventional clock buffer polarity assignment methods, which are: 1) the unawareness of the signal delay (i.e., arrival time) differences to the leaf clock buffering elements; 2) the ignorance of the effect of the current fluctuation of nonleaf clock buffering elements on the total peak current waveform; and 3) the inability of supporting low-power digital designs with multiple (dynamically operating) power modes. Clearly, not addressing 1 and 2 in the polarity assignment may cause a severe inaccuracy on the peak current estimation, which results in unnecessarily high peak current. Moreover, without tackling 3, designs may suffer from clock skew violation in some of the power modes, affecting circuit speed or reliability. To overcome the limitations, we propose a completely new fine-grained approach to the clock buffer polarity assignment combined with buffer sizing, formulating the problem into a multiobjective shortest path problem and solving it effectively for designs with a single power mode, while exploiting the flexibility of our multiobjective shortest path formulation for designs with multiple power modes. Through experiments using benchmark circuits, it is shown that the proposed approach is able to produce designs with 17% lower peak current and 20% lower power noise on average, compared with the results produced by the best ever known method.

An Adaptive Thread Scheduling Mechanism With Low-Power Register File for Mobile GPUs

In response to the remarkable increase in 3D applications in consumer electronics devices in recent years, graphics processing units (GPUs) have become widely available on mobile devices. These GPUs typically use hardware multithreaded shaders to improve their throughputs for real-time rendering, but they depend on duplicate register files to maintain the context of each hardware thread, increasing power consumption. However, the register usage of shading programs is often relatively low, which causes many registers to remain unused, thus wasting power. Long latency memory operations can also consume unnecessary power to activate registers. This study proposes a low-power register file with multiple power modes to reduce the power consumption of the register file. This study also presents an adaptive thread scheduling mechanism to achieve a tradeoff between the power consumption of the register file and frames per second (FPS). Results show that the average performance degradation from the proposed low-power register file is only 0.62%. The proposed adaptive thread scheduling has average under prediction ratio of 3.32%. The leakage reduction of the proposed low-power register file is 74.80%. This reduction can be improved to 81.49%, 82.22%, and 84.28% with adaptive thread scheduling at frame rates of 30, 25, and 20, respectively.

An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs

Satisfying a clock skew constraint is one of the most important tasks in clock tree synthesis. Moreover, the task becomes much harder to solve when the clock tree is designed in a multiple power mode environment, in which the voltage applied to some design module varies as the power mode changes. Recently, it has been shown that an adjustable delay buffer (ADB), whose delay can be tuned dynamically, can be used to solve the clock skew problem effectively under multiple power modes. However, due to the area or control overhead by ADBs, it is very important to minimize the number of ADBs to be allocated. This paper provides a complete solution to the problem of clock skew optimization using ADBs under multiple power modes. We propose a linear-time algorithm that simultaneously solves the problems of computing: 1) the minimum (optimal) number of ADBs to be used; 2) the location where each ADB is to be placed; and 3) the delay value of each ADB to be assigned to each power mode. Experimental results show that, in comparison with the previous work, which iteratively performs the ADB allocation, placement, and value assignment, our integrated algorithm produces consistently better designs for all tested benchmarks; it reduces the numbers of ADBs by 9.27% on average under the skew bound of 30-50 ps, even with shorter clock latencies compared to that of previous algorithm of ADB allocation, placement, and delay assignment. To make it practically feasible, we also propose a new ADB design technique and systematic algorithmic solutions to address the problems of discrete delay values, slew rate variation, nonzero initial ADB delay, and a possible exploration of ADB resizing.

Energy-efficient carpool policy for wireless interfaces of mobile devices in ubiquitous environments

Nowadays, power consumption is a big concern for mobile devices because battery power of mobile devices is one of the most crucial resources. Unfortunately, the performance of battery power fails to meet the power needs of high-end mobile devices. Increased data to be transferred/received through wireless communication incur high power consumption, because the wireless communication interface is one of the most dominant modules of mobile devices in terms of power consumption. Therefore, efficient power management of wireless interfaces should be employed for mobile devices. Dynamic power management is widely employed in order to support multiple power modes such as active modes (e.g., transmit, receive, and idle mode) and inactive modes (e.g., sleep mode and power off). Therefore maximizing the staying time of the wireless interface in an inactive mode is an essential scheme to reduce energy expenditure. However, required overhead energy and time for turning on/off the wireless interface are not negligible. Most of recent works have been trying to enhance the hardware architecture or network/MAC protocols. In this paper, we present an energy-efficient carpool policy that turns on the wireless interface and transmits all awaited data only when the predefined threshold is exceeded. We propose two kinds of thresholds–time and space. For practical evaluation, we conduct not only simulations but also experimental measurements by implementing a test program on a real test bed. Results of simulation and experimental measurements show that our proposed scheme incurs less energy expenditure than legacy power management schemes do.

A wireless sensor network for precision agriculture and its performance

ABSTRACTThe use of wireless sensor networks is essential for implementation of information and control technologies in precision agriculture. We present our design of network stack for such an application where sensor nodes periodically collect data from fixed locations in a field. Our design of the physical layer consists of multiple power modes in both the receive and transmit operations for the purpose of achieving energy savings. In addition, we design our MAC layer to use these multiple power modes to improve the energy efficiency of wake‐up synchronization phase. Our MAC protocol also organizes all the sender nodes to be synchronized with the receiver simultaneously and transmit their data in a time scheduled manner. Next, we design our energy aware routing strategy that balances the energy consumption over the nodes in the entire field and minimizes the number of wake‐up synchronization overheads by scheduling the nodes for transmission in accordance with the structure of the routing tree. We develop analytical models and simulation studies to compare the energy consumption of our MAC protocol with that of the popular S‐MAC protocol for a typical network topology used in our application under our routing strategy. Our MAC protocol is shown to have better energy efficiency as well as latency in a periodic data collection application. We also show the improvements resulting from the use of our routing strategy, in simulations, compared with the case when the next hop is chosen randomly from the set of neighbors that are closer to the sink node. Copyright © 2011 John Wiley &amp; Sons, Ltd.

Dynamic buffer management using optimal control of hybrid systems

This paper studies a dynamic buffer management problem with one buffer inserted between two interacting components. The component to be controlled is assumed to have multiple power modes corresponding to different data processing rates. The overall system is modeled as a hybrid system and the buffer management problem is formulated as an optimal control problem. Different from many previous studies, the objective function of the proposed problem depends on the switching cost and the size of the continuous state space, making its solution much more challenging. By exploiting some particular features of the problem, the best mode sequence and the optimal switching instants are characterized analytically using a variational approach. Simulation results based on real data shows that the proposed method can significantly reduce the energy consumption compared with another heuristic scheme in several typical situations.

Multimode power modeling and maximum-likelihood estimation

It is known that circuits exhibit multiple modes of power consumption due to various factors such as the presence of many feedback (or sequential) elements, RAM, large size, etc. Previous power-estimation techniques have largely ignored this fact. For example, Monte Carlo simulation-based power estimators tend to produce estimates for the average power consumption that corresponds only to the most probable power mode of the circuit. This can be a cause for trouble later in the design step. The aim of this paper is twofold. First, an algorithm is proposed that estimates the total number of power modes of a circuit based on simulated data. This is then followed by a maximum-likelihood estimation procedure that produces the average values of the power modes along with their probabilities of occurrence. Theoretical ideas are supported by experimental results for ISCAS '85 benchmark circuits and a large industrial circuit. The proposed method is shown to perform well by capturing the multiple power modes for both large and small circuits even when the number of simulated samples is small while the Monte Carlo estimator does not. We conclude with a note that the proposed method is also applicable to other model selection problems in VLSI.