Multiple LUTs Research Articles

Asynchronous logiс one-level LUT design based on partial acknowledgement

In the paper, asynchronous logic design targeting LUT of custom size (number of inputs) implementation is proposed. It is based on conventional Sum-Of-Product terms (SOP) what differs from existing methods where Sum-Of-Minterms (SOM) and Disjoint SOP are supposed. It is shown, that LUT architectural features and delays ensure SOP hazard-free implementation. Nowadays reconfigurable chips contain multiple LUTs that can be combined using so called dedicated multiplexers. It implies producing LUT-based structure of various inputs number to match design needs. As a result, a function can be implemented using one-level LUT which increases the circuit performance. It is in contrast to the conventional approach where multi-level implementation is supposed. The model consists of functional and completion detection (CD) blocks. Both blocks are implemented using LUTs. LUTs total size is an optimization criterion. The method of LUTs total size minimization is proposed where inputs are removed from CD block and partially acknowledged via functional one. The problem is formulated as a covering task. Two sets of benchmarks are processed and comparison is done. Using our method, improvement w.r.t mention criterion is achieved.

LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet Classification

This paper presents a packet classifier using multiple LUT cascades for edge-valued multi-valued decision diagrams (EVMDDs $(k)$ ). Since the proposed one uses both DSP blocks and on-chip memories, it can efficiently use the available FPGA resources. Thus, it can realize a parallel packet classifier on a single-chip FPGA for the next generation 400 Gb/s Internet link rate (IEEE 802.3). Since it is a memory-based one, the power consumption is lower than the TCAM-based one. Also, we proposed an on-line update method that can be done without intermitting the packet classification. Compared with the conventional off-line update which requires resynthesis of the re-generated HDL codes, it drastically reduces the update time. Although the proposed on-line update requires additional hardware, the overhead is only 8.5% of the original LUT cascades, which is acceptable. We implemented a two-parallel packet classifier on a Virtex 7 VC707 evaluation board. The system throughput is 640 Gb/s for minimum packet size (40 Bytes). For the performance per memory, the proposed architecture is 2.21 times higher than existing methods. For the power consumption per performance, the proposed architecture is 11.95 times lower than existing methods.

FPGA based Hardware Implementation of Variant DPCM Image Compression Technique (Multiple LUT-DPCM)

This paper proposed FPGA implementation of variant DPCM based image compression technique (Multiple LUT-DPCM). Image compression addresses the problem of reducing the amount of data required to represent a digital image. Such data compression can be achieved by reducing the redundancies of the image data in order to be able to store or transmit data in an efficient form. There are various onboard data compression techniques used in image processing. Out of which DPCM based compression technique is the most commonly used one. For the hardware implementation, an algorithm for Multiple LUT DPCM is designed. VHDL code is developed based on the algorithm designed. After simulation and verification of developed code with test data generated, it implemented in to hardware. The developed hardware’s functionality, then verified with the already simulated data and also with real image data.

The impact of lower urinary tract symptoms on male sexual health: EpiLUTS

To evaluate the association between International Continence Society categories of lower urinary tract symptoms (LUTS; storage, voiding, and postmicturition) and individual LUTS (associated with decreased sexual activity and sexual satisfaction in men) with erectile dysfunction (ED), ejaculatory dysfunction (EjD) and premature ejaculation (PE). The impact of LUTS on men's sexual health was captured as part of a cross-sectional epidemiological study to assess the prevalence LUTS among men and women aged > or =40 years in the USA, the UK and Sweden. The analysis included 11 834 men with a mean age of 56.1 years, 71% of whom reported being currently sexually active. The primary reason for not being sexually active was no partner (35%), followed by personal health (23%) and no desire (23%). Of the men, 26% had mild to severe ED, 7% had EjD, and 16% PE. Men with multiple LUTS had more severe ED and more frequent EjD and PE. Logistic regression analysis showed that greater age, hypertension, diabetes, depression, urgency with fear of leaking, and leaking during sexual activity were significantly associated with ED. The results were similar in the logistic regression analysis for EjD, whereas being younger and the absence of prostatitis were significantly associated with PE, as were the presence of terminal dribble, incomplete emptying, and split stream. LUTS are associated with common sexual dysfunctions in men. The results of this study highlight the importance of assessing the sexual health of men presenting with LUTS.

Prevalence, Severity, and Symptom Bother of Lower Urinary Tract Symptoms among Men in the EPIC Study: Impact of Overactive Bladder

BackgroundLower urinary tract symptoms (LUTS) are prevalent among men. ObjectiveTo describe the prevalence, severity, and symptom bother of LUTS in all men and men with overactive bladder (OAB) symptoms in the EPIC study. Design, setting, and participantsA secondary analysis of data from EPIC, a multinational population-based survey of 19 165 adults, was performed. Current International Continence Society definitions were used for individual LUTS and OAB; OAB cases were defined as men reporting urgency. MeasurementsParticipants were asked about the presence of individual LUTS and associated symptom bother. LUTS severity was measured using the International Prostate Symptom Score (IPSS). Results and limitationsThere was substantial overlap of storage, voiding, and postmicturition symptoms among all men (n=7210) and in men with OAB symptoms (n=502); men with OAB symptoms were more likely to experience multiple LUTS subtypes. Among both populations, nocturia was the most commonly reported symptom, except for urgency (the hallmark symptom) among men with OAB symptoms; terminal dribble and sensation of incomplete emptying were the most common voiding and postmicturition symptoms. The prevalence of all LUTS increased with age among the general population; only storage LUTS increased with age among men with OAB symptoms. Number of LUTS and mean IPSS increased with age in both populations but were higher among men with OAB symptoms at all ages; the proportion reporting moderate–severe LUTS was higher than the general population (30% vs 6%). The proportion of men with OAB symptoms reporting symptom bother increased with urgency severity and severity and number of LUTS. LUTS severity may have been underestimated by the IPSS, which does not assess incontinence. ConclusionsMen with LUTS commonly experience coexisting storage, voiding, and postmicturition symptoms, emphasizing the need for comprehensive urologic assessments. Men with OAB symptoms reported more LUTS and greater severity than the general population. Symptom bother was related to number of LUTS and urgency severity.

On the design of LPM address generators using multiple LUT cascades on FPGAs

We propose the multiple LUT cascade as a way to configure an n-input longest prefix match (LPM) address generator commonly used in routers to determine the output port given an address. The LPM address generator accepts n-bit addresses which it matches against k stored prefixes. We implement our design on a Xilinx Spartan-3 FPGA for n = 32 and k=504∼511. Also, we compare our design to a Xilinx proprietary ternary content-addressable memory (TCAM) design and to another design we propose as a likely solution to this problem. Our best multiple LUT cascade implementation has 5.17 times more throughput, 40.71 times more throughput/area and is 2.97 times more efficient in terms of area-delay product than Xilinx's proprietary design, but its area is only 15% of Xilinx's design. Furthermore, we derive a method to determine the optimum configuration of the multiple LUT cascade on an FPGA.