LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet Classification

Abstract

This paper presents a packet classifier using multiple LUT cascades for edge-valued multi-valued decision diagrams (EVMDDs $(k)$ ). Since the proposed one uses both DSP blocks and on-chip memories, it can efficiently use the available FPGA resources. Thus, it can realize a parallel packet classifier on a single-chip FPGA for the next generation 400 Gb/s Internet link rate (IEEE 802.3). Since it is a memory-based one, the power consumption is lower than the TCAM-based one. Also, we proposed an on-line update method that can be done without intermitting the packet classification. Compared with the conventional off-line update which requires resynthesis of the re-generated HDL codes, it drastically reduces the update time. Although the proposed on-line update requires additional hardware, the overhead is only 8.5% of the original LUT cascades, which is acceptable. We implemented a two-parallel packet classifier on a Virtex 7 VC707 evaluation board. The system throughput is 640 Gb/s for minimum packet size (40 Bytes). For the performance per memory, the proposed architecture is 2.21 times higher than existing methods. For the power consumption per performance, the proposed architecture is 11.95 times lower than existing methods.