Multiple Instruction Stream-multiple Data Stream Research Articles

New Reconfigurable Memory Architecture for Parallel Image-Processing LSI with Three-Dimensional Structure

A reconfigurable memory network for a parallel image-processing LSI with a three-dimensional structure is proposed. The proposed memory network can be dynamically configured by changing the connections between processing elements (PEs) and memories in accordance with the required part of the stored image data. In addition, a specification of the data bandwidth between PEs and the proposed memory network can be changed in the synchronization with single instruction stream-multiple data stream (SIMD) and multiple instruction stream-multiple data stream (MIMD) operations. Therefore, data transfer has greater flexibility. Also, from the result of the performance evaluation by implementation into the field programmable gate array (FPGA), it was successfully shown that the proposed memory network reduced the execution time by up to 28.2% for a 9×9 filtering operation.

Right-Brain/Left-Brain Integrated Associative Processor Employing Convertible Multiple-Instruction-Stream Multiple-Data-Stream Elements

A very large scale integrated circuit (VLSI) architecture for a multiple-instruction-stream multiple-data-stream (MIMD) associative processor has been proposed. The processor employs an architecture that enables seamless switching from associative operations to arithmetic operations. The MIMD element is convertible to a regular central processing unit (CPU) while maintaining its high performance as an associative processor. Therefore, the MIMD associative processor can perform not only on-chip perception, i.e., searching for the vector most similar to an input vector throughout the on-chip cache memory, but also arithmetic and logic operations similar to those in ordinary CPUs, both simultaneously in parallel processing. Three key technologies have been developed to generate the MIMD element: associative-operation-and-arithmetic-operation switchable calculation units, a versatile register control scheme within the MIMD element for flexible operations, and a short instruction set for minimizing the memory size for program storage. Key circuit blocks were designed and fabricated using 0.18 µm complementary metal-oxide-semiconductor (CMOS) technology. As a result, the full-featured MIMD element is estimated to be 3 mm2, showing the feasibility of an 8-parallel-MIMD-element associative processor in a single chip of 5 mm×5 mm.

A parallel computing engine for a class of time critical processes

This paper focuses on the efficient parallel implementation of systems of numerically intensive nature over loosely coupled multiprocessor architectures. These analytical models are of significant importance to many real-time systems that have to meet severe time constants. A parallel computing engine (PCE) has been developed in this work for the efficient simplification and the near optimal scheduling of numerical models over the different cooperating processors of the parallel computer. First, the analytical system is efficiently coded in its general form. The model is then simplified by using any available information (e.g., constant parameters). A task graph representing the interconnections among the different components (or equations) is generated. The graph can then be compressed to control the computation/communication requirements. The task scheduler employs a graph-based iterative scheme, based on the simulated annealing algorithm, to map the vertices of the task graph onto a Multiple-Instruction-stream Multiple-Data-stream (MIMD) type of architecture. The algorithm uses a nonanalytical cost function that properly considers the computation capability of the processors, the network topology, the communication time, and congestion possibilities. Moreover, the proposed technique is simple, flexible, and computationally viable. The efficiency of the algorithm is demonstrated by two case studies with good results.

Boundary element analysis by Krylov subspace method on MIMD parallel multiprocessor system

The parallel boundary element solution on a distributed-memory multiprocessor computer is presented. The proposed computational strategy does not require the formulation of the system of boundary element equations explicitly. According to the number of processors of the MIMD (multiple instruction stream-multiple data stream) parallel computer, the total boundary element nodes are divided into the same number of groups and distributed to each processor which stores relevant information and generates corresponding boundary element equations. The Krylov subspace method is employed to solve in parallel the system of boundary element equations that are distributed in the processors. The results of boundary element analysis, i.e. strain and stress of internal points are also given by each processor in parallel.

Assessing Programming Costs of Explicit Memory Localization on a Large Scale Shared Memory Multiprocessor

We present detailed experimental work involving a commercially available large scale shared memory multiple instruction stream‐multiple data stream (MIMD) parallel computer having a software controlled cache coherence mechanism. To make effective use of such an architecture, the programmer is responsible for designing the program′s structure to match the underlying multiprocessors capabilities. We describe the techniques used to exploit our multiprocessor (the BBN TC2000) on a network simulation program, showing the resulting performance gains and the associated programming costs. We show that an efficient implementation relies heavily on the user′s ability to explicitly manage the memory system.

Development of a Parallelism Analysis Integrated System for a Fast-Running Pressurized Water Reactor Plant Predictive Simulator

This paper reports on a parallelism analysis integrated system (PARIS) with a multiple instruction stream-multiple data stream (MIMD) scheme developed to analyze simulation programs and generate a parallel execution program for parallel processing. This simulation program can predict effects of anomalies in nuclear plants. The PARIS system first analyzes task parallelism and the processing time of each task after a user divides a program developed for a single processor into many elementary assignment units. The system then assigns tasks to processors using the critical path/most immediate successor first scheduling algorithm to minimize the overall processing time, and it generates the parallel execution program, which can be executed with a tightly coupled multiprocessor. The PARIS system has two scheduling methods so it can assign tasks to the multiprocessor both before and during execution of the program.

Process groups and group communications: classifications and requirements

An attempt is made to place recent architectural innovations in the broader context of parallel architecture development by surveying the fundamentals of both newer and more established parallel computer architectures and by placing these architectural alternatives in a coherent framework. The primary emphasis is on architectural constructs rather than specific parallel machines. Three categories of architecture are defined and discussed: synchronous architectures, comprising vector, SIMD (single-instruction-stream, multiple-data-stream) and systolic machines; MIMD (multiple-instruction-stream, multiple-data-stream) with either distributed or shared memory; and MIMD-based paradigms, comprising MIMD/SIMD hybrid, dataflow, reduction, and wavefront types. >

Efficient and correct execution of parallel programs that share memory

In this paper we consider an optimization problem that arises in the execution of parallel programs on shared-memory multiple-instruction-stream, multiple-data-stream (MIMD) computers. A program on such machines consists of many sequential program segments, each executed by a single processor. These segments interact as they access shared variables. Access to memory is asynchronous, and memory accesses are not necessarily executed in the order they were issued. An execution is correct if it is sequentially consistent: It should seem as if all the instructions were executed sequentially, in an order obtained by interleaving the instruction streams of the processors. Sequential consistency can be enforced by delaying each access to shared memory until the previous access of the same processor has terminated. For performance reasons, however, we want to allow several accesses by the same processor to proceed concurrently. Our analysis finds a minimal set of delays that enforces sequential consistency. The analysis extends to interprocessor synchronization constraints and to code where blocks of operations have to execute atomically. We use a conflict graph similar to that used to schedule transactions in distributed databases. Our graph incorporates the order on operations given by the program text, enabling us to do without locks even when database conflict graphs would suggest that locks are necessary. Our work has implications for the design of multiprocessors; it offers new compiler optimization techniques for parallel languages that support shared variables.

A multiminiprocessor system implemented through pipelining

Several recent and proposed computer systems have employed parallel and pipelined architectures to increase instruction execution rate, or throughput. These vary from the giant ILLIAC IV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> with its large number of processing elements constrained to perform nearly identical computations in unison (single instruction stream-multiple data stream <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> ) to the Carnegie-Mellon C. mmp system <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> employing a number of independent minicomputers with shared memory (multiple instruction stream-multiple data stream). On the other hand, pipelining has been used in numerous' large computers, such as the Control Data 6600, 7600, and STAR, the IBM System 360/91 and 360/195, and the Texas Instruments ASC, to improve throughput. These systems generally employ single instruction stream-single data stream processing, although some machines in this category also have “vector” instructions that operate on multiple data streams.

Very high-speed computing systems

Very high-speed computers may be classified as follows: 1) Single Instruction Stream-Single Data Stream (SISD) 2) Single Instruction Stream-Multiple Data Stream (SIMD) 3) Multiple Instruction Stream-Single Data Stream (MISD) 4) Multiple Instruction Stream-Multiple Data Stream (MIMD). Stream, as used here, refers to the sequence of data or instructions as seen by the machine during the execution of a program. The constituents of a system: storage, execution, and instruction handling (branching) are discussed with regard to recent developments and/or systems limitations. The constituents are discussed in terms of concurrent SISD systems (CDC 6600 series and, in particular, IBM Model 90 series), since multiple stream organizations usually do not require any more elaborate components. Representative organizations are selected from each class and the arrangement of the constituents is shown.