Abstract
Several recent and proposed computer systems have employed parallel and pipelined architectures to increase instruction execution rate, or throughput. These vary from the giant ILLIAC IV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> with its large number of processing elements constrained to perform nearly identical computations in unison (single instruction stream-multiple data stream <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> ) to the Carnegie-Mellon C. mmp system <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> employing a number of independent minicomputers with shared memory (multiple instruction stream-multiple data stream). On the other hand, pipelining has been used in numerous' large computers, such as the Control Data 6600, 7600, and STAR, the IBM System 360/91 and 360/195, and the Texas Instruments ASC, to improve throughput. These systems generally employ single instruction stream-single data stream processing, although some machines in this category also have “vector” instructions that operate on multiple data streams.
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