Current-mode CMOS analog defuzzification circuits previously proposed are insensitive to absolute variation of the fabrication process and are easy to expand into a multiple-input circuit. However, they have two disadvantages. One is that they need two input currents which are equal in magnitude and opposite in direction (sign). A current steering circuit which consists of current mirrors is used for changing the direction of the input current signals. However, because current mirrors are strongly influenced by channel length modulation effect, it is very difficult to generate the desired current signal. The other disadvantage is that they need input bias currents for all input signals, which causes high power consumption. In this paper, a current-mode CMOS analog four-quadrant multiplier for defuzzification circuits is proposed. The proposed multiplier is insensitive to absolute variation of the fabrication process. Furthermore, it removes the above disadvantages. A defuzzification circuit using the proposed multiplier is designed. The proposed defuzzification circuit is improved to reduce power dissipation by using a common bias block circuit. These circuits are analyzed in detail by the PSPICE System. The proposed defuzzification circuit is evaluated and its validity is discussed. © 1997 Scripta Technica, Inc. Electron Comm Jpn Pt 3, 80(6): 30–41, 1997