Multiple Field Programmable Gate Array Research Articles

GLRM: Geometric Layout-Based Resource Management Method on Multiple Field Programmable Gate Array Systems

Multiple field programmable gate array (Multi-FPGA) systems are capable of forming larger and more powerful computing units through high-speed interconnections between chips and are beginning to be widely used by various computing service providers. However, the new computing architecture brings new challenges to the system’s task resource management. Existing resource management methods do not fully exploit resources in Multi-FPGA systems, and it is difficult to support fast resource request and release. In this regard, we propose a geometric layout-based resource management (GLRM) method for Multi-FPGA systems. First, a geometric layout-based task combination algorithm (TCA) was proposed to ensure that the final system can use the available FPGA resources more efficiently. Then, we optimised two resource management algorithms using TCA. Compared with state-of-the-art resource management methods, TCA increases resource flexibility by an average of 6% and resource utilisation by an average of 7%, and the two optimised resource management methods are effective in improving resource management performance.

High-Level Synthesis Design of Scalable Ultrafast Ultrasound Beamformer With Single FPGA.

Ultrafast ultrasound imaging is essential for advanced ultrasound imaging techniques such as ultrasound localization microscopy (ULM) and functional ultrasound (fUS). Current ultrafast ultrasound imaging is challenged by the ultrahigh data bandwidth associated with the radio frequency (RF) signal, and by the latency of the computationally expensive beamforming process. As such, continuous ultrafast data acquisition and beamforming remain elusive with existing software beamformers based on CPUs or GPUs. To address these challenges, the proposed work introduces a novel method of implementing an ultrafast ultrasound beamformer specifically for ultrafast plane wave imaging (PWI) on a field programmable gate array (FPGA) by using high-level synthesis. A parallelized implementation of the beamformer on a single FPGA was proposed by 1) utilizing a delay compression technique to reduce the delay profile size, which enables both run-time pre-calculated delay profile loading from external memory and delay reuse, 2) vectorizing channel data fetching which is enabled by delay reuse, and 3) using fixed summing networks to reduce consumption of logic resources. Our proposed method presents two unique advantages over current FPGA beamformers: 1) high scalability that allows fast adaptation to different FPGA resources and beamforming speed demands by using Xilinx High-Level Synthesis as the development tool, and 2) allow a compact form factor design by using a single FPGA to complete the beamforming instead of multiple FPGAs. Current Xilinx FPGAs provide the capabilities of connecting up to 1024 ultrasound channels with a single FPGA and the newest JESD204B interface analog front end (AFE). This channel count is much more than the channel count needed by current linear arrays, which normally have 128 or 256 channels. With the proposed method, a sustainable average beamforming rate of 4.83 G samples/second in terms of input raw RF sample was achieved. The resulting image quality of the proposed beamformer was compared with the software beamformer on the Verasonics Vantage system for both phantom imaging and in vivo imaging of a mouse brain. Multiple imaging schemes including B-mode, power Doppler and ULM were assessed to verify that the image quality was not compromised for speed.

Faster-Than-Real-Time Hardware Emulation of Extensive Contingencies for Dynamic Security Analysis of Large-Scale Integrated AC/DC Grid

The rapid expansion of modern power systems has brought a tremendous computational challenge to dynamic security analysis (DSA) tools which consequently need to process extensive contingencies. In this work, hardware emulation is investigated to accelerate the DSA solution of a large-scale AC/DC system deployed on the field-programmable gate arrays (FPGAs) faster-than-real-time (FTRT) execution. Electromagnetic transient (EMT) modeling of the DC grid is conducted since the fast converter dynamics require a small time-step for accuracy; in contrast, the transient stability (TS) simulation is applicable to the AC grid which tolerates a much larger step size. To coordinate the 2 different types of simulation, an interface based on dynamic voltage injection is proposed to integrate the AC and DC grids, in addition to maintaining a low hardware latency. An emulation platform consisting of multiple FPGA boards is established so that with a proper allocation it has a sufficient capacity to accommodate the system under study which has 6 ACTIVSg 500-bus systems interconnected by a 6-terminal DC grid. The efficacy of the proposed FTRT hardware emulation platform is demonstrated by 2 case studies with more than 5500 contingencies analyzed in total, where an FTRT ratio of more than 208 is achieved for the hybrid AC/DC grid, while it is over 277 times for a single 500-bus system. Furthermore, the FTRT dynamic emulation results, including the security indices, are validated by the simulation tool DSATools/TSAT.

Highly Parallel Multi-FPGA System Compilation from Sequential C/C++ Code in the AWS Cloud

We present a High Level Synthesis compiler that automatically obtains a multi-chip accelerator system from a single-threaded sequential C/C++ application. Invoking the multi-chip accelerator is functionally identical to invoking the single-threaded sequential code the multi-chip accelerator is compiled from. Therefore, software development for using the multi-chip accelerator hardware is simplified, but the multi-chip accelerator can exhibit extremely high parallelism. We have implemented, tested, and verified our push-button system design model on multiple field-programmable gate arrays (FPGAs) of the Amazon Web Services EC2 F1 instances platform, using, as an example, a sequential-natured DES key search application that does not have any DOALL loops and that tries each candidate key in order and stops as soon as a correct key is found. An 8- FPGA accelerator produced by our compiler achieves 44,600 times better performance than an x86 Xeon CPU executing the sequential single-threaded C program the accelerator was compiled from. New features of our compiler system include: an ability to parallelize outer loops with loop-carried control dependences, an ability to pipeline an outer loop without fully unrolling its inner loops, and fully automated deployment, execution and termination of multi-FPGA application-specific accelerators in the AWS cloud, without requiring any manual steps.

Fast Energy-Optimal Multikernel DNN-Like Application Allocation on Multi-FPGA Platforms

Platforms with multiple Field Programmable Gate Arrays (FPGAs), such as Amazon Web Services (AWS) F1 instances, can efficiently accelerate multi-kernel pipelined applications, e.g., Convolutional Neural Networks for machine vision tasks or transformer networks for Natural Language Processing tasks. To reduce energy consumption when the FPGAs are underutilized, we propose a model to (1) find off-line the minimum-power solution for given throughput constraints, and (2) dynamically reprogram the FPGA at runtime (which is complementary to dynamic voltage and frequency scaling) to match best the workloads when they change. The off-line optimization model can be solved using a Mixed-Integer Non-Linear Programming (MINLP) solver, but it can be very slow. Hence, we provide two heuristic optimization methods that improve result quality within a bounded time. We use several very large designs to demonstrate that both heuristics obtain comparable results to MINLP, when it can find the best solution, and they obtain much better results than MINLP, when it cannot find the optimum within a bounded amount of time. The heuristic methods can also be thousands of times faster than the MINLP solver.

Accelerating parallel data processing using optically tightly coupled FPGAs

A cutting-edge field programmable gate array (FPGA) card can be equipped with high-bandwidth inputs and outputs by high-density optical integration, e.g., onboard Si-photonics transceivers or co-packaged optics. It is possible to implement highly parallel data processing by using tightly coupled FPGAs. We previously proposed a lightweight, fully connected inter-FPGA network called OPTWEB for efficient collective communications. OPTWEB discards the traditional packet communication mechanism and introduces dedicated memory processing to minimize communication overhead. In this paper, we provide the design guidelines for a parallel data application on FPGAs connected by OPTWEB. We then present a generalized diameter-two hypercube network topology for connecting multiple FPGAs, which enables larger applications. In the guidelines, data to be exchanged should be directly processed by the dedicated memory on each FPGA, and parallelism should be implemented to match the collective communications provided by OPTWEB. We illustrate two case studies, one on parallel counting sort and the other on sharing averaged parameters, on eight custom Stratix10 MX2100 FPGA cards with 800 Gbps network bandwidth. The parallel counting sort operates up to 5.3 times faster than a comparable CPU cluster with the conventional InfiniBand network, and with sharing averaged parameters, up to 250 times faster operation is achieved. The two applications utilize a total of 80.1% and 60.6% of the adaptive logic modules of the FPGA, respectively.

Machine Learning Based Transient Stability Emulation and Dynamic System Equivalencing of Large-Scale AC-DC Grids for Faster-Than-Real-Time Digital Twin

Modern power systems have been expanding significantly including the integration of high voltage direct current (HVDC) systems, bringing a tremendous computational challenge to transient stability simulation for dynamic security assessment (DSA). In this work, a practical method for energy control center with the machine learning (ML) based synchronous generator model (SGM) and dynamic equivalent model (DEM) is proposed to reduce the computational burden of the traditional transient stability (TS) simulation. The proposed ML-based models are deployed on the field programmable gate arrays (FPGAs) for faster-than-real-time (FTRT) digital twin hardware emulation of the real power system. The Gated Recurrent Unit (GRU) algorithm is adopted to train the SGM and DEM, where the training and testing datasets are obtained from the off-line simulation tool DSAToolsTM/TSAT®. A test system containing 15 ACTIVSg 500-bus systems interconnected by a 15-terminal DC grid is established for validating the accuracy of the proposed FTRT digital twin emulation platform. Due to the complexity of emulating large-scale AC-DC grid, multiple FPGA boards are applied, and a proper interface strategy is also proposed for data synchronization. As a result, the efficacy of the hardware emulation is demonstrated by two case studies, where an FTRT ratio of more than 684 is achieved by applying the GRU-SGM, while it reaches over 208 times for hybrid computational-ML based digital twin of AC-DC grid.

Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning

Customized compute acceleration in the datacenter is key to the wider roll-out of applications based on deep neural network (DNN) inference. In this article, we investigate how to maximize the performance and scalability of field-programmable gate array (FPGA)-based pipeline dataflow DNN inference accelerators (DFAs) automatically on computing infrastructures consisting of multi-die, network-connected FPGAs. We present Elastic-DF, a novel resource partitioning tool and associated FPGA runtime infrastructure that integrates with the DNN compiler FINN. Elastic-DF allocates FPGA resources to DNN layers and layers to individual FPGA dies to maximize the total performance of the multi-FPGA system. In the resulting Elastic-DF mapping, the accelerator may be instantiated multiple times, and each instance may be segmented across multiple FPGAs transparently, whereby the segments communicate peer-to-peer through 100 Gbps Ethernet FPGA infrastructure, without host involvement. When applied to ResNet-50, Elastic-DF provides a 44% latency decrease on Alveo U280. For MobileNetV1 on Alveo U200 and U280, Elastic-DF enables a 78% throughput increase, eliminating the performance difference between these cards and the larger Alveo U250. Elastic-DF also increases operating frequency in all our experiments, on average by over 20%. Elastic-DF therefore increases performance portability between different sizes of FPGA and increases the critical throughput per cost metric of datacenter inference.

Multichannel gas electron multiplier based soft x-ray field-programmable gate array measurement system for W-Environment in Steady-state Tokamak (WEST): Hardware, installation, and first plasma acquisition.

The work describes a novel approach to the design of a fast, multichannel measurement system for plasma diagnostics [A. Wojenski et al., Fusion Eng. Des. 123, 727 (2016)]. Its main scope is to provide measurements of soft X-ray (SXR) emission during plasma phenomena at the W-Environment in Steady-state Tokamak (WEST), especially for monitoring and tracing tungsten impurities. This paper describes the vertical Gas Electron Multiplier (GEM) camera installed at the WEST [M. Chernyshova et al., J. Instrument. 10, P10022 (2015)]. The designed GEM detector readout board has more than 100 channels, resulting in high-performance requirements for the data acquisition and processing system. The novel system construction approach is that the unit works on the raw signals providing a high quality of the data, especially in the scope of pileup effect analysis. In the case of doubtful results, the source data can be easily reviewed offline. The data selection and transmission are done in Field-Programmable Gate Arrays (FPGAs) on the custom boards with the custom Peripheral Component Interconnect (PCI)-Express Gen2 switch that allows us to register signals from multiple FPGAs and then process the data by complex algorithms [G. Kasprowicz et al., J. Fusion Energy 38, 480 (2019)]. The firmware is replaceable and different working modes can be applied (some under verification): global trigger mode, high-speed data serialization, and extended signal registration. Low level optimized central processing unit software for data readout was also designed [P. Linczuk et al., J. Instrum. 14, C05001 (2019)]. The installation of the system is described due to complex system components' distribution. The first results of the successful acquisition of the plasma at the WEST are discussed. The corresponding SXR energy and topology spectra were computed. Those are the first technical measurements of the system to ensure verification of data quality.

Combining Multiple Optimized FPGA-based Pulsar Search Modules Using OpenCL

Field-Programmable Gate Arrays (FPGAs) are widely used in the central signal processing design of the Square Kilometer Array (SKA) as hardware accelerators. The frequency domain acceleration search (FDAS) module is an important part of the SKA1-MID pulsar search engine. To develop for a yet to be finalized hardware, for cross-discipline interoperability and to achieve fast prototyping, OpenCL as a high-level FPGA synthesis approaches employed to create the sub-modules of FDAS. The FT convolution and the harmonic-summing plus some other minor sub-modules are elements in the FDAS module that have been well-optimized separately before. In this paper, we explore the design space of combining well-optimized designs, dealing with the ensuing need to trade-off and compromise. Pipeline computing is employed to handle multiple input arrays at high speed. The hardware target is to employ multiple high-end FPGAs to process the combined FDAS module. The results show interesting consequences, where the best individual solutions are not necessarily the best solutions for the speed of a pipeline where FPGA resources and memory bandwidth need to be shared. By proposing multiple buffering techniques to the pipeline, the combined FDAS module can achieve up to 2[Formula: see text] speedup over implementations without pipeline computing. We perform an extensive experimental evaluation on multiple high-end FPGA cards hosted in a workstation and compare to a technology comparable mid-range GPU.

A 1 Million-Point FFT on a Single FPGA

In this paper, we present the first implementation of a 1 million-point fast Fourier transform (FFT) completely integrated on a single field-programmable gate array (FPGA), without the need for external memory or multiple interconnected FPGAs. The proposed architecture is a pipelined single-delay feedback (SDF) FFT. The architecture includes a specifically designed 1 million-point rotator with high accuracy and a thorough study of the word length at the different FFT stages in order to increase the signal-to-quantization-noise ratio (SQNR) and keep the area low. This also results in low power consumption.

Experimental Quantification of Hardware Requirements for FPGA-Based Reconfigurable PMUs

Phasor Measurement Units (PMUs) are becoming intrinsic components of modern power systems. The synchrophasor estimation algorithms in PMUs pose stringent computational demands, which makes the application of Field Programmable Gate Arrays (FPGA) highly attractive. Previous works reported the implementation of PMU algorithms on specific FPGA-targets using a particular PMU design. This paper explores the implementation of different PMU designs on multiple FPGA targets using Xilinx and NI software and hardware infrastructures and toolsets. In this process, a metric has been formulated to predict FPGA-target hardware requirements. The metric allows predicting if an FPGA-target meets the needs to deploy a given PMU design resulting in significant engineering design time savings. Since the compilation/synthesis on FPGAs is a time-consuming job, this metric can reduce the implementation time for FPGA-based PMUs drastically and can help in determining if additional functionalities can be added.

High speed CMOS acquisition system based on FPGA embedded image processing for electro-optical measurements

Electro-optical measurements, i.e., optical waveguides and plasmonic based electrochemical impedance spectroscopy (P-EIS), are based on the sensitive dependence of refractive index of electro-optical sensors on surface charge density, modulated by an AC electrical field applied to the sensor surface. Recently, P-EIS has emerged as a new analytical tool that can resolve local impedance with high, optical spatial resolution, without using microelectrodes. This study describes a high speed image acquisition and processing system for electro-optical measurements, based on a high speed complementary metal-oxide semiconductor (CMOS) sensor and a field-programmable gate array (FPGA) board. The FPGA is used to configure CMOS parameters, as well as to receive and locally process the acquired images by performing Fourier analysis for each pixel, deriving the real and imaginary parts of the Fourier coefficients for the AC field frequencies. An AC field generator, for single or multi-sine signals, is synchronized with the high speed acquisition system for phase measurements. The system was successfully used for real-time angle-resolved electro-plasmonic measurements from 30 Hz up to 10 kHz, providing results consistent to ones obtained by a conventional electrical impedance approach. The system was able to detect amplitude variations with a relative variation of ±1%, even for rather low sampling rates per period (i.e., 8 samples per period). The PC (personal computer) acquisition and control software allows synchronized acquisition for multiple FPGA boards, making it also suitable for simultaneous angle-resolved P-EIS imaging.

ULA-OP 256: A 256-Channel Open Scanner for Development and Real-Time Implementation of New Ultrasound Methods.

Open scanners offer an increasing support to the ultrasound researchers who are involved in the experimental test of novel methods. Each system presents specific performance in terms of number of channels, flexibility, processing power, data storage capability, and overall dimensions. This paper reports the design criteria and hardware/software implementation details of a new 256-channel ultrasound advanced open platform. This system is organized in a modular architecture, including multiple front-end boards, interconnected by a high-speed (80 Gb/s) ring, capable of finely controlling all transmit (TX) and receive (RX) signals. High flexibility and processing power (equivalent to 2500 GFLOP) are guaranteed by the possibility of individually programming multiple digital signal processors and field programmable gate arrays. Eighty GB of on-board memory are available for the storage of prebeamforming, postbeamforming, and baseband data. The use of latest generation devices allowed to integrate all needed electronics in a small size ( 34 cm ×30 cm ×26 cm). The system implements a multiline beamformer that allows obtaining images of 96 lines by 2048 depths at a frame rate of 720 Hz (expandable to 3000 Hz). The multiline beamforming capability is also exploited to implement a real-time vector Doppler scheme in which a single TX and two independent RX apertures are simultaneously used to maintain the analysis over a full pulse repetition frequency range.

Parallel Genetic Algorithms on Multiple FPGAs

Genetic algorithms (GA) have been shown to be effective in the optimization of many large-scale real-world problems in a reasonable amount of time. Parallel GAs not only reduce the overall GA execution time, but also bring higher quality solutions due to parallel search in multiple parts of the solution space. This paper proposes a parallel GA system on hardware such as Field-Programmable-Gate-Arrays (FPGAs). Our approach targets multiple FPGAs by exploring different search areas of the same solution space with different behaviours. Each FPGA contains an optimised customisable GA which can be configured using run-time parameters, removing the need for expensive recompilation. This paper also explores adjustment of the migration gap, providing empirical guidance on good settings to users. Experiments on three problems show the high performance of our system, with a 30 times speedup achieved compared to a multi-core CPU-based implementation.

A Multidimensional Configurable Processor Array — Vocalise

SUMMARY A processing system with multiple field programmable gate array (FPGA) cards is described. Each FPGA card can interconnect using six I/O (up, down, left, right, front, and back) terminals. The communication network among FPGAs is scalable according to user design. When the system operates multi-dimensional applications, transmission efficiency among FPGA improved through user-adjusted dimensionality and network topologies for different applications. We provide a fast and flexible circuit configuration method for FPGAs of a multi-dimensional FPGA array. To demonstrate the effectiveness of the proposed method, we assess performance and power consumption of a circuit that calculated 3D Poisson equations using the finite difference method.

Application of GRAPE9-MPX for High Precision Calculation in Particle Physics and Performance Results

Abstract There are scientific applications which require calculations with high precision such as Feynman loop integrals and orbital integrations. These calculations also need to be accelerated. We have been developing dedicated accelerator systems which consist of processing elements (PE) for high precision arithmetic operations and a programing interface. GRAPE9-MPX is our latest system with multiple Field Programmable Gate Array (FPGA) boards on which our developed PEs are implemented. We present the performance results for GRAPE9-MPX extended to have up to 16 FPGA boards for quadruple, hexuple, and octuple precision calculation. The achieved performance for a Feynman loop integral with 12 FPGA boards is 26.5 Gflops for quadruple precision, 13.2 Gflops for hexuple precision, and 6.36 Gflops for octuple precision. We show that our hardware implementation is 80 - 200 times faster than software implementations. We also give analysis of the performance results.

FPGA Security: Motivations, Features, and Applications

Since their inception, field-programmable gate arrays (FPGAs) have grown in capacity and complexity so that now FPGAs include millions of gates of logic, megabytes of memory, high-speed transceivers, analog interfaces, and whole multicore processors. Applications running in the FPGA include communications infrastructure, digital cinema, sensitive database access, critical industrial control, and high-performance signal processing. As the value of the applications and the data they handle have grown, so has the need to protect those applications and data. Motivated by specific threats, this paper describes FPGA security primitives from multiple FPGA vendors and gives examples of those primitives in use in applications.

Multi-FPGA Accelerator for Scalable Stencil Computation with Constant Memory Bandwidth

Stencil computation is one of the important kernels in scientific computations. However, sustained performance is limited owing to restriction on memory bandwidth, especially on multicore microprocessors and graphics processing units (GPUs) because of their small operational intensity. In this paper, we present a custom computing machine (CCM), called a scalable streaming-array (SSA), for high-performance stencil computations with multiple field-programmable gate arrays (FPGAs). We design SSA based on a domain-specific programmable concept, where CCMs are programmable with the minimum functionality required for an algorithm domain. We employ a deep pipelining approach over successive iterations to achieve linear scalability for multiple devices with a constant memory bandwidth. Prototype implementation using nine FPGAs demonstrates good agreement with a performance model, and achieves 260 and 236 GFlop/s for 2D and 3D Jacobi computation, which are 87.4 and 83.9 percent of the peak, respectively, with a memory bandwidth of only 2.0 GB/s. We also evaluate the performance of SSA for state-of-the-art FPGAs.

Hardware Emulation Building Blocks for Real-Time Simulation of Large-Scale Power Grids

This paper proposes digital hardware building block concept for emulating power system networks on field-programmable gate arrays (FPGAs) in real time. Basic hardware emulation building blocks (HEBBs) for machines, transmission lines, nonlinear elements, and loads are presented to demonstrate how real-time simulation can be achieved for realistic power systems. All of the hardware modules were developed using the VHDL language for portability and extensibility. Employing multiple FPGAs, a large-scale power system consisting of 1260 three-phase buses is modeled in detail in real time to show both electromagnetic transients and electromechanical dynamics in the system. The advantage of HEBB-based modeling is that the design and development of new technologies can be accelerated by utilizing massive real-time digital simulators capable of modeling multiscale and multidomain dynamics.