Multiple Error Detection Research Articles

Multiple error detection and identification via signature analysis

Signature analysis has been used widely for fault detection as a part of Built-In Self Test (BIST). In this paper we show how signature analysis can be used not only for fault detection but also for identification of multiple errors produced by faults in the circuits under test. We construct Signature Analysis Registers (SARs) to detect and identify any specified number of errors in the input polynomials by choosing proper characteristic polynomials. To detect and identifyr errors in an input bit stream ofm bits, we use a polynomialg r (x)=1cm (f 1 (x), f 3 (x), ..., f 2r−1 (x)) as the characteristic polynomial for the SAR for any polynomialf 1 (x), where lcm represents the least common multiple of polynomials al $$fi(x) = Res_t (f_1 (t),x - t^i ), i = 3,...,2r - 1,$$ Res t denotes thet-Resultant, andm is less than the order off 1 (x). Given a faulty signature produced by an SAR constructed as described, we present an algorithm for the identification of the actual error bits in the input polynomial to the SAR. We also extend the use of BCH codes for error detection and correction to include nonprimitive polynomials.

On multiple error detection in matrix triangularizations using checksum methods

We introduced a unified checksum method for multiple transient error detection in three different matrix triangularizations: the LU decomposition, Gaussian elimination with pairwise pivoting, and the QR decomposition. We first develop the theoretical back-ground for multiple error detection in matrix triangularizations, and summarize the results by providing that we can detect all the transient errors that occur in a maximum of t different columns by introducing t checksum vectors. A floating-point error analysis, to determine the effects of the rounding errors in using the checksum method for multiple error detection and correction, is also presented.

A coding theory approach to error control in redundant residue number systems. II. Multiple error detection and correction

For pt.I see ibid., vol.39, no.1, p.8-17 (1992). The coding theory approach to error control in redundant residue number systems (RRNSs) is extended by deriving computationally efficient algorithms for correcting multiple errors, single-burst-error, and detecting multiple errors. These algorithms reduce the computational complexity of the previously known algorithms by at least an order of magnitude.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A well conditioned checksum scheme for algorithmic fault tolerance

The weighted checksum scheme has been proposed as a low-cost fault tolerant procedure for parallel matrix computations. To guarantee multiple error detection and correction, the chosen weight vectors must satisfy some very specific properties about linear independence. However, previous weight generating methods that fulfill the independence criteria have troubles with numerical overflow. We will present a new scheme that generates weight vectors via Chebyshev polynomials to meet the requirements about independence and to avoid the difficulties with overflow.

Single error correcting and multiple unidirectional error detecting cyclic an arithmetic codes

We present cyclic AN arithmetic codes capable of single error correction and multiple unidirectional error detection. These codes can be used throughout a fault-tolerant computer, and they eliminate the need for encoding/decoding circuits and code translation circuits. We use criteria for the determination of the unidirectional error detection capability for a given AN code, and we present a new error correction/detection scheme.

A Note on `` A Note on Multiple Error Detection in ASCII Numeric Data Communication''

article Free AccessA Note on `` A Note on Multiple Error Detection in ASCII Numeric Data Communication'' Author: D. V. Sarwate Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, 1101 West Springfield Avenue, Urbana, IL Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, 1101 West Springfield Avenue, Urbana, ILView Profile Authors Info & Claims Journal of the ACMVolume 30Issue 1Jan. 1983 pp 33–35https://doi.org/10.1145/322358.322361Published:01 January 1983Publication History 1citation289DownloadsMetricsTotal Citations1Total Downloads289Last 12 Months11Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Serial Coding for Cyclic Block Codes

In 1972 the concept of seriol encoding and decoding for single, error correcting BCH codes was introduced. <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1,2</sup> In this note, the concept of serial encoding and decoding is generolized and the timing diagrams are presented for a typical (n, k) cyclic block code. The implementation in conventional tecnology uses only one exclusive-OR gate and is presented for all (n - k) order generator polynomials for any code n bits long. The implementations presented are valid for all eyclic block encoders and for all decoders with single error correction with multiple error detection capability.

Detection of Unidirectional Multiple Errors Using Low-Cost Arithmetic Codes

We show that a low-cost arithmtetic code with group length n detects all unidirectional multiple errors that affect fewer than n bits, as well as a larger class of such errors confined to a restricted set of bit positions.

Modeling of a Bubble-Memory Organization with Self-Checking Translators to Achieve High Reliability

This paper reports a study on the design and modeling of a highly reliable bubble-memory system. This system has the capability of correcting a single 16-adjacent bit-group error resulting from failures in a single basic storage module (BSM), and detecting with a probability greater than 0.99 any double errors resulting from failures in BSM's. The encoding/decoding network (memory translator) is designed to be self-checking, i.e., a single circuit failure in the translator wiH not produce an erroneous output that goes undetected. The system is able to perform reliable configuration in the event of uncorrectable BSM failures, memory translator failures, and dual-memory buffer failures; even in the presence of a single failure in the status registers controlling the configuration network. The bubble memory under study permits serial accessing of the store with 64 x 1024 bit blocks at a 100-kHz rate. The objective of this study is to develop good fault-tolerant design and analysis methods adequate for newly emerging technologies and prove the practicality by example. The reliability modeling study justifies the design philosophy adopted of employing memory data encoding and a translator to correct single group errors and detect double group errors to enhance the overall system reliability. By a proper design of the memory translator based on a new checking technique, a uniformly high percentage of multiple b-adjacent bit-group error detection is achieved through the use of a proposed code (detects 99.99695 percent of double b-adjacent bit-group errors and 99.9985 percent of triple or more b-adjacent bit-group errors).