Multiple Constant Multiplication Research Articles

Difference Adder Graph Algorithm for Reducing LUT Size

The current study introduces an implementation of the Difference Adder Graph Algorithm (DAGA) using Verilog. DAGA, rooted in graph theory and adder circuits, aims to diminish Look Up Tables (LUTs) and power consumption in Field Programmable Gate Arrays (FPGAs). By reducing the number of LUTs required for a specific functionality, DAGA offers a promising alternative for digital circuit optimization. To evaluate its efficacy, the paper contrasts DAGA with the Multiple Constant Multiplication (MCM) method, which leverages Carry Save Adder (CSA) architecture and exploits signed-digit number representations to minimize LUT usage. Experimental findings reveal DAGA's superiority over MCM in both area and power utilization reduction. Implementation details and results indicate a remarkable 49.29% reduction in LUT count and a corresponding 41.8% decrease in power consumption for digital circuits. These outcomes underscore the effectiveness of DAGA in enhancing FPGA efficiency, highlighting its potential as a valuable tool for digital circuit designers seeking to optimize performance and power utilization.

Flexible FPGA 1D DCT hardware architecture for HEVC

In this work, we propose a flexible 1D DCT hardware design with a constant throughput of 32 pixels per cycle for all transform block (TB) size modes. The design supports all TB sizes defined in the HEVC standard. Flexibility is achieved by multiplexing only the outputs, which results in lower data path delays compared to other proposed designs. Also, the additional partial butterfly units are transferred to the output of transformation cores. The transformation operation is done in a single stage to minimize the latency of the design and reduce hardware usage. The highly parallel input reduces the need for a very high operational frequency, which is suitable for low-power FPGA designs. Four different reusable transformation cores are used that are designed using parallel Multiple Constant Multiplication (MCM) units to further reduce the calculation time. The design was implemented on the Virtex UltraScale + device. The implementation has hardware usage of 21,818 LUTs, and it can reach the maximal throughput of 4.90 Gsps at the working frequency of 153 MHz which is enough to support the video resolutions of up to 8192 × 4320@60fps. Comparison with the other works shows that DCT FPGA implementation without DSPs can reach the performance of the ASICs with trade-offs in power consumption.

Toward the Multiple Constant Multiplication at Minimal Hardware Cost

Multiple Constant Multiplication (MCM) over integers is a frequent operation arising in embedded systems that require highly optimized hardware. An efficient way is to replace costly generic multiplication by bit-shifts and additions, i.e. a multiplierless circuit. In this work, we improve the state-of-the-art optimal approach for MCM, based on Integer Linear Programming (ILP). We introduce a new low-level hardware cost metric, which counts the number of one-bit adders and demonstrate that it is strongly correlated with the LUT count. This new model permitted us to consider intermediate truncations that permit to significantly save resources when a full output precision is not required. We incorporate the error propagation rules into our ILP model to guarantee a user-given error bound on the MCM results. The proposed ILP models for multiple flavors of MCM are implemented as an open-source tool and, combined with an automatic code generator, provide a complete coefficient-to-VHDL flow. We evaluate our models in extensive experiments, and propose an in-depth analysis of the impact that design metrics have on synthesized hardware.

ICARUS

The practical deployment of Neural Radiance Fields (NeRF) in rendering applications faces several challenges, with the most critical one being low rendering speed on even high-end graphic processing units (GPUs). In this paper, we present ICARUS, a specialized accelerator architecture tailored for NeRF rendering. Unlike GPUs using general purpose computing and memory architectures for NeRF, ICARUS executes the complete NeRF pipeline using dedicated plenoptic cores (PLCore) consisting of a positional encoding unit (PEU), a multi-layer perceptron (MLP) engine, and a volume rendering unit (VRU). A PLCore takes in positions & directions and renders the corresponding pixel colors without any intermediate data going off-chip for temporary storage and exchange, which can be time and power consuming. To implement the most expensive component of NeRF, i.e., the MLP, we transform the fully connected operations to approximated reconfigurable multiple constant multiplications (MCMs), where common subexpressions are shared across different multiplications to improve the computation efficiency. We build a prototype ICARUS using Synopsys HAPS-80 S104, a field programmable gate array (FPGA)-based prototyping system for large-scale integrated circuits and systems design. We evaluate the power-performancearea (PPA) of a PLCore using 40nm LP CMOS technology. Working at 400 MHz, a single PLCore occupies 16.5 mm 2 and consumes 282.8 mW, translating to 0.105 uJ/sample. The results are compared with those of GPU and tensor processing unit (TPU) implementations.

Multiplication and Accumulation Co-Optimization for Low Complexity FIR Filter Implementation

In multiplierless finite impulse response (FIR) filters, the product accumulation block (PAB) could be the major contributor to hardware complexity, especially for high-order filters. In this paper, an optimization scheme where the constant multiplication block and the PAB are jointly optimized at the bit-level is proposed to minimize the hardware complexity. In the proposed joint optimization, the multiple constant multiplications (MCM) block is rearranged into several MCM sub-blocks. The products are summed locally before accumulation to reduce the word-length of the structural adders. It is shown that the symmetric property of linear phase FIR filters can be utilized in some cases to further reduce the complexity of the constant multiplications. Quantitative analyses are also presented to study the relationship between the optimum group size and the coefficient values as well as the filter orders. It is shown that there is no fixed optimum structure for filters with different coefficient word-lengths and filter orders, and each filter needs to be optimized specifically to achieve the minimum hardware complexity. Implementation results are presented to validate the effectiveness of the proposed method.

Unified Multiple Constant Multipliers for Dynamic Exchange of Low-Precision Kernels on FPGAs

Recent work has shown that small, fast, and power-efficient multiple constant multiplication (MCM) implementations can be realized on FPGAs rather than requiring specialized embedded multipliers. However, the limited silicon area on FPGAs requires applications such as image processing to frequently exchange the multiplier (filter) blocks in a series of filtering operations, and no previous works have considered the MCM problem under topological constraint to avoid time-consuming partial reconfiguration on FPGAs. In this paper, we define a unified MCM (UMCM) problem of finding a unified hardware topology for the multiplier blocks frequently exchanged and introduce a framework termed compatible graph synthesis to solve the problem efficiently. Using a set of parameters to logarithmic shifters, dynamic exchange of multiplier blocks with the unified topology can be realized without partial reconfiguration on FPGAs. Experimental results show that the solution is valuable for applications that require frequent exchange of multiplier blocks on FPGAs due to a limited silicon area budget.

Exploring Multi-Level Composition and Efficient MCM Schemes for an Energy-Efficient Wavelet Haar Architecture

This work explores multi-level fixed-point Haar transform compositions combined with MCM (multiple constant multiplication) schemes for an energy-efficient hardware architecture. We investigate a set of six lower-level Haar transforms for composing a Haar-9 architecture. The multiple-level Haar transforms use as a base M=1, M=2, and M=3 resolution levels. The processing module (PM) of the Haar explores efficient MCM schemes. The architectures were described in VHDL and synthesized employing the ST 65nm CMOS cell library. The results show that Haar-II architecture presents the lower circuit area results since this architecture requires fewer arithmetic operators. However, the most energy-efficient Haar-9 hardware architecture employs a combination of two M=2 with five M=1 blocks with a efficient MCM architecture reduced to only two arithmetic operators.

Radix‐2 r recoding with common subexpression elimination for multiple constant multiplication

In a recent work on multiple constant multiplication (MCM) problems, a fully predictable sub-linear runtime heuristic was introduced, called Radix-2 r MCM. This method shows competitive results in speed, power and area, comparatively with the leading algorithms. In this study, the authors combine Radix-2 r MCM with an exact common subexpression elimination (CSE) algorithm. The resulting algorithm denoted Radix-2 r -CSE allows a substantial reduction in the number of addition/subtraction operations in MCM by maximising the sharing of partial terms after an initial recoding in Radix-2 r MCM. The savings over Radix-2 r MCM ranges from 4.34 to 18.75% (10% on average) when considering a set of 14 benchmark finite impulse response filters of varying complexity.

High-Speed FIR Filter Design using Decision Tree Algorithm with FPGA Debugging

In recent years, the filter is one of the key elements in signal processing applications to remove unwanted information. However, traditional FIR filters have been consumed more resources due to complex multiplier design. Mostly the complexity of the FIR filter is dominated by multiplier design. The conventional multipliers can be realized by Single Constant Multiplication (SCM) and Multiple Constant Multiplication (MCM) algorithms using shift and add/subtract operations. In this paper, a hybrid state decision tree algorithm is introduced to reduce hardware utilization (area) and increase speed in filter tap cells of FIR. The proposed scheme generates a decision tree to perform shift & addition and accumulation based on the combined SCM/MCM approach. The proposed FIR filter was implemented in Xilinx Field Programmable Gate Array (FPGA) platform by using Verilog language. The experimental results of the DTG-FIR filter were averagely reduced the 48.259% of LUTs, 51.567 % of flip flops and 44.497 % of slices at 183.122 MHz of operating frequency on the Virtex-5 than existing VP-FIR.

Architectures for multiple constant decimal multiplication

Due to the increasing demand for decimal calculations in the business, financial and economic world, decimal arithmetic circuits have been much considered by system designers. This is mainly because, these applications heavily depend on decimal arithmetic since the results must match exactly those obtained by human calculations. While decimal multiplication is one of the most frequent and complex-to-implement decimal operations, the special case of constant decimal multiplication is widely used in the economic and financial applications. In this paper, we propose two ideas, named “Constant Decimal TCSD” (CDT) and “Constant Decimal DDDS” (CDD), and their hardware implementations for realizing multiple constant decimal multiplication. In the CDT and CDD architectures, the partial products are generated using a set of positive multiplicand multiples coded in2′s complement signed-digit format (TCSD) and binary coded decimal (BCD), respectively. We also present two new (3:1) compressors to reduce the number of partial products in both designs, one based on a new Double Decimal Digit Set (DDDS), which is not only self-complementing but also its redundancy, allows carry-free addition. Finally, a redundant to non-redundant converter recodes the TCSD and DDDS product to BCD in the first and second schemes, respectively. Hardware synthesis evaluation shows that compared to the most recent 16 × 16 decimal multipliers, delay, area, power consumption and PDP of the proposed multiple constant multipliers improve up to 57%, 89%, 93% and 97%, respectively.

A fast realization of new Mersenne number transformation and its applications

SummaryThe new Mersenne number transform (NMNT) can be realized by the fast Fourier transform (FFT) with power‐of‐two length, which results in great flexibility in real‐world fixed‐point computations, such as the convolution‐based signal processing in the embedded device. Yet the FFT realization exists the truncation errors and in order to further reduce the computations, this paper puts forward a novel realization structure for the NMNT, where the Walsh‐Hadamard transform (WHT) is employed to accelerate the NMNT computation. Moreover, we also propose the refined computing structure using the matrix decomposition and multiple constant multiplication (MCM), and then all multiplications can be replaced by the shift‐addition operations without precision loss. Besides, the use of lookup table (LUT) to reduce the complexity is also discussed in our study. A typical convolution application is tested by computer simulations, while the result demonstrates that the proposed scheme produces precise computing results with reduced complexity.

A High-Performance FIR filter Architecture for Reconfigurable Applications

Transpose form finite-impulse response (FIR) filters are characteristically pipelined and support multiple constant multiplications (MCM) procedure that results in significant saving of calculation. However, transpose form configuration does not specifically support the block performing not like direct-form configuration. In this paper, we investigate the possibility of realization of block FIR filter in transpose shape configuration for area-delay efficient realization of huge order FIR filters for both fixed applications. Based on a detailed computational investigation of transpose form configuration of FIR filter, we have derived a flow diagram for transpose shape block FIR filter with reduced register complexity. A detailed block formulation is detailed for transpose form FIR filter. We have inferred a general multiplier-based architecture for the proposed transpose form block filter for reconfigurable applications. A reduced-complex design using multiple constant multiplications scheme is also showed for block implementation of fixed FIR filters. The proposed architecture obtains less area, less delay and less power consumption compared with the existing architecture of direct form structure for medium or long filter lengths. For this project analysis for determining area, power and delay it uses Xilinx.

Efficient Shift-Add Implementation of FIR Filters Using Variable Partition Hybrid Form Structures

Single constant multiplication (SCM) and multiple constant multiplications (MCM) are among the most popular schemes used for low-complexity shift-add implementation of finite impulse response (FIR) filters. While SCM is used in the direct form realization of FIR filters, MCM is used in the transposed direct form structures. Very often, the hybrid form FIR filters where the sub-sections are implemented by fixed-size MCM blocks provide better area, time, and power efficiency than those of traditional MCM and SCM based implementations. To have an efficient hybrid form filter, in this paper, we have performed a detailed complexity analysis in terms of the hardware and time consumed by the hybrid form structures. We find that the existing hybrid form structures lead to an undesirable increase of complexity in the structural-adder block. Therefore, to have a more efficient implementation, a variable size partitioning approach is proposed in this paper. It is shown that the proposed approach consumes less area and provides nearly 11% reduction of critical path delay, 40% reduction of power consumption, 15% reduction of area-delay product, 52% reduction of energy-delay product, and 42% reduction of power-area product, on an average, over the state-of-the-art methods.

Resource minimization and power reduction of ESPFFIR filter using unified adder/subtractor

Digital filters are the important processing elements in most of the digital signal processing system designs, ranging from medical signal processing to wireless communication. Low power and area efficient Finite Impulse Response filter is designed with the aid of parallel processing which increases the throughput. Symmetric property reduces the multipliers into half in Even Symmetric Parallel Fast Finite Impulse Response (ESPFFIR) filters. The adder and the subtractor present in the pre/post-processing blocks increase in accordance with the block size L of ESPFFIR filter which in turn increases the numbers of unified operators. The canonical signed digit representation of the coefficient in the design Multiple Constant Multiplications (MCM) based multipliers has the advantages of utilizing unified operators in sub-filter block of ESPFFIR. To reduce the power consumption and resource utilization of the ESPFFIR filter, the unified operator used in the pre/post processing and MCM blocks are replaced by unified adder subtractor (UAS). The UAS utilizes fewer resources for simultaneous calculation of sum and difference of two operands with less area and low power consumption. This paper shows the design of 16-bit Square Root (SQRT) UAS CSLA adder using UAS logical element to reduce the area utilization, power consumption and delay. Then the Heuristic of cumulative benefit (Hcub) based MCM multiplier is designed using UAS. The existing SQRT BEC CSLA adder and subtractor with same input present in the pre/post processing block of the ESPFFIR filters are replaced by a single SQRT UAS CSLA in suitable places. The Hcub MCM used in the sub-filter blocks of the ESPFFIR are replaced using SQRT UAS CSLA based MCM multiplier. The SQRT UAS CSLA consumes 78% less area, 29.51% less power and 24% less delay when compared to the BEC CSLA 2 (one BEC based CSLA Adder plus one BEC based CSLA Subtractor). Finally, the SQRT UAS CSLA adder and Hcub based UAS MCM multipliers are used to design the filter, the overall area and power consumption of UAS based ESPFFIR is reduced compared with the existing BEC based ESPFFIR filter. Cadence RC tool is used for analysis.

Survey: Performance Analysis of FIR Filter Design Using Modified Truncation Multiplier with SQRT based Carry Select Adder

A recent years of technology development in Signal processing application a FIR (Finite impulse response) filter design will have a highly compactable with high performance and low power in all digital signal processing application, such as audio processing, signal processing, software define radio and so on. Now a days in our environment will have more signal noises, and fluctuation due to technology development, here the Filter design is mainly configuring the priority to reduce the signal noises and fluctuation in all type of gadgets. In this project, the design contains Transpose form of high performance and high speed filter design using finite impulse response (FIR) filter with technique of pipelined inherently and supported multiple constant multiplication (MCM) in significant with saving power computation. In digital signal processing, the multiplier is a highly required thing, the example of parallel multiplier provide a high-speed and highly reliable method for multiplication, but this parallel multiplier will take large area and also power consumption. In the FIR filter design, multiplier and adders is the maximum priority will take to give the performance, but this MCM multiplier and Adders tree architecture will take large area and maximum power consumption in signal processing. So our Proposed approach of this work, will have replace the MCM multiplier to Truncated Multiplier and using the technique of Truncated based both Signed and Unsigned Operation with SQRT based Carry Select Adder (CSLA), and also replace the normal adders in FIR Filter to SQRT based Carry Select Adder (CSLA). In the proposed system of FIR Filter design results to be analysis with signed and unsigned Truncation using modified technique of HSCG-SCS based SQRT-CSLA and hence proved its more efficient than existing design, such as FIR filter for Truncation multiplier with SQRT-CSLA based Adders, FIR filter for Truncation multiplier with BEC based Adders, FIR filter for Truncation multiplier with RCA, and FIR filter for Truncation multiplier with Common Boolean logic based RCA, and finally implemented this design on VHDL with help of Xilinx FPGA-S6LX9 and shown the performance of proposed design in terms of delay, area, and power.

Algorithms for Multiplierless Multiple Constant Multiplication in Online Arithmetic

Online arithmetic operators offer advantages of reduction in resource utilization and interconnection complexity besides providing pipelining at digit level. Multiplierless constant coefficient multiplication using the shift-and-add technique is widely used in digital signal processing applications. This paper proposes a novel bit serial adaptation of the parallel shift-and-add algorithm to online arithmetic. The proposed multipliers use right shifts instead of the traditional left shifts resulting in causal online implementations. Graph-based and hybrid algorithms are developed for the estimation of the distance of a constant from a set of constants in terms of the number of additions and for the synthesis of online multiple constant multipliers under area and online delay constraints. The computational complexity of the algorithms is determined. Results of implementation on randomly generated constant sets and FIR filter instances show substantial improvements in the number of operations required using the distance heuristic. Further, it is shown that the proposed techniques and algorithms result in significant savings in resource utilization, logic depth, and clock frequency compared to parallel and digit-serial algorithms.

Design of high performance filter bank multi-carrier transmitter

Filter bank multi-carrier (FBMC) is very important to achieve high spectral efficiency in the wireless communication process. Previously, orthogonal frequency division multiplexing (OFDM) technique is used to obtain a high spectral efficiency. But area, power and delay is high than the FBMC transmitter technique. The main aim of this work is to design an optimized FBMC transmitter for high speed, low power and low area applications. There is a tradeoff between power and speed. To overcome this challenge, a new compact FBMC transmitter will be introduced in the paper. Generally, the FBMC transmitter consists of serial to parallel converter, QAM modulation, inverse FFT, parallel to serial converter and filter. The existing FBMC transmitter is designed by using inverse radix 2 FFT and poly phase filter. It requires more area, power and delay. To overcome this problem, a new radix2 multipath delay commutator (R2MDC) based inverse FFT and multiple constant multiplication (MCM) based FIR filter are used in the proposed FBMC transmitter. Because MCM based FIR filter doesn’t needs multiplier structure. The multiplication process is done by shift, add and subtract operation. Hence area and power is low in MCM based FIR filters, when compared to poly base filter. Also R2MDC FFT is used for high speed application. Comparison between conventional FBMC transmitter and proposed FBMC transmitter is carried out to analyze the performance, area, complexity and power. Also the functionality of FBMC transmitter is verified by using Xilinx ISE Virtex5 device. From the comparison results, it shows that the proposed FBMC transmitter offers 17% average area, delay and power (ADP) product than the existing FBMC transmitter.

Design of high‐speed, low‐power, and area‐efficient FIR filters

In a recent work, we have introduced a new multiple constant multiplication (MCM) algorithm, denoted as RADIX-2 r . The latter exhibits the best results in speed and power, comparatively with the most prominent algorithms. In this paper, the area aspect of RADIX-2 r is more specially investigated. RADIX-2 r is confronted to area efficient algorithms, notably to the cumulative benefit heuristic (Hcub) known for its lowest adder-cost. A number of benchmark FIR filters of growing complexity served for comparison. The results showed that RADIX-2 r is better than Hcub in area, especially for high order filters where the saving ranges from 1.50% up to 3.46%. This advantage is analytically proved and experimentally confirmed using a 65nm CMOS technology. Area efficiency is achieved along with important savings in speed and power, ranging from 6.37% up to 38.01% and from 9.30% up to 25.85%, respectively. When MCM blocks are implemented alone, the savings are higher: 10.18%, 47.24%, and 41.27% in area, speed, and power, respectively. Most importantly, we prove that MCM heuristics using similar addition pattern (A-operation with the same shift spans) as Hcub yield excessive bit-adder overhead in MCM problems of high complexity. As such, they are not competitive to RADIX-2 r in high order filters.

Optimization of Constant Matrix Multiplication with Low Power and High Throughput

Constant matrix multiplication (CMM), i.e., the multiplication of a constant matrix with a vector, is a common operation in digital signal processing. It is a generalization of multiple constant multiplication (MCM) where a single variable is multiplied by a constant vector. Like MCM, CMM can be reduced to additions/subtractions and bit shifts. Finding a circuit with minimal number of add/subtract operations is known as the CMM problem. While this leads to a reduction in circuit area it may be less efficient for power consumption or throughput. It is well studied for the MCM problem that a) reducing the adder depth (AD) leads to a reduced power consumption and b) pipeline resources have to be considered during optimization to enhance throughput without wasting area. This paper addresses the optimization of CMM circuits which considers both adder depth and pipelining for the first time. For that, a heuristic is proposed which evaluates the most attractive graph topologies. It is shown that the proposed method requires 12.5% less adders with min. AD and 38.5% less pipelined operations. Synthesis results for recent FPGAs show that these reductions also translate to superior results in terms of delay and power consumption compared to the state-of-the-art.

Reduced-Area Constant-Coefficient and Multiple-Constant Multipliers for Xilinx FPGAs with 6-Input LUTs

Multiplication by a constant is a common operation for many signal, image, and video processing applications that are implemented in field-programmable gate arrays (FPGAs). Constant-coefficient multipliers (KCMs) are often implemented in the logic fabric using lookup tables (LUTs), reserving embedded hard multipliers for general-purpose multiplication. This paper describes a two-operand addition circuit from previous work and shows how it can be used to generate and add pre-computed partial products to implement KCMs. A novel method for pre-computing partial products for KCMs with a negative constant is also presented. These KCMs are then extended to have two to eight coefficients that may be selected by a control signal at runtime to implement time-multiplexed multiple-constant multiplication. Synthesis results show that proposed pipelined KCMs use 27.4% fewer LUTs on average and have a median LUT-delay product that is 12% lower than comparable LogiCORE IP KCMs. Proposed pipelined KCMs with two to eight selectable coefficients use 46% to 70% fewer LUTs than the best LogiCORE IP based alternative and most are faster than using a LogiCORE IP multiplier with a coefficient lookup function. They also outperform the state-of-the-art in the literature, using 22% to 57% fewer slices than the smallest pipelined adder graph (PAG) fusion designs and operate 7% to 30% faster than the fastest PAG fusion designs for the same operand size and number of selectable coefficients. For KCMs and KCMs with selectable coefficients of a given operand size, the placement and routing of LUTs remains the same for all positive and negative constant values, which is advantageous for runtime partial reconfiguration.