A High-Performance FIR filter Architecture for Reconfigurable Applications

Abstract

Transpose form finite-impulse response (FIR) filters are characteristically pipelined and support multiple constant multiplications (MCM) procedure that results in significant saving of calculation. However, transpose form configuration does not specifically support the block performing not like direct-form configuration. In this paper, we investigate the possibility of realization of block FIR filter in transpose shape configuration for area-delay efficient realization of huge order FIR filters for both fixed applications. Based on a detailed computational investigation of transpose form configuration of FIR filter, we have derived a flow diagram for transpose shape block FIR filter with reduced register complexity. A detailed block formulation is detailed for transpose form FIR filter. We have inferred a general multiplier-based architecture for the proposed transpose form block filter for reconfigurable applications. A reduced-complex design using multiple constant multiplications scheme is also showed for block implementation of fixed FIR filters. The proposed architecture obtains less area, less delay and less power consumption compared with the existing architecture of direct form structure for medium or long filter lengths. For this project analysis for determining area, power and delay it uses Xilinx.