Multiple Clock Domains Research Articles

Implementation of a Multiclocked Pipelined Processor Based on RISc-V using RV321

This study's primary objective is to create a 32-bit pipelined processor based on the open-source RV32I Version 2.0 RISC-V ISA that operates across several clock domains. A processor known as a RISC (Reduced Instruction Set Computer) employs less hardware than a CISC (Complex Instruction Set Computer) in order to reduce the complexity of the instruction set and accelerate the execution time per instruction. In addition, we built this processor with five pipelining layers, which allows for concurrent processing of instructions. All of the procedures are thoroughly explained, supported with the required block diagrams. To guarantee that variable delays, such as clock skew and meta-stability, are avoided inside the stage pipeline registers, multiple clock domains using two clock sources are employed.

Classification of Sequential Circuits as Causal Functions

In sequential circuits, the current output can depend on both past and current inputs. However, certain kinds of sequential circuits do not refer to all of the past inputs to generate the current output; but only to a subset of past inputs. This paper investigates which subset of past inputs a sequential circuit refers to, and proposes a new classification of sequential circuits based on this criterion. While the conventional classification of sequential circuits distinguishes between synchronous and asynchronous circuits, the new classification consolidates synchronous circuits and multiple clock domain circuits into the same category. This is consistent with the notion that “multiple clock domain circuits are analogous to synchronous circuits,” and thus, the proposed classification appears valid from this perspective. It is expected that a method underlying our classification will allow a deeper understanding of sequential circuits.

Metastability in Superconducting Single Flux Quantum (SFQ) Logic

Superconducting digital electronics, especially Single Flux Quantum (SFQ), has emerged as a promising beyond-CMOS technology with Josephson junctions (JJ) as the active device. It has the potential to meet the booming demands of lower power consumption and higher operation speeds in the electronics industry and future exascale supercomputing systems. Despite these promises, scaling SFQ circuits remains a serious challenge that motivates the support of multiple SFQ clock domains. Towards this end, this paper analyzes the impact of setup time violations and metastability in SFQ circuits comparing the derived analytical models to their CMOS counterparts. It also proposes new techniques to reduce the average latency in metastability-tolerant SFQ synchronizers, and evaluates their effects on the layout and critical margin of the design. It further extends the proposed model to estimate the Mean Time Between Failure (MTBF) of flip-flop-based synchronizers and shows that their MTBF with the current feature sizes is unaffected by noise, similar to CMOS. Finally, it curve fits this model to simulations using the state-of-the-art SFQ5ee process and shows that a two-flop SFQ synchronizer with a clock frequency of 25 GHz has an estimated MTBF of ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> years.

Single Flux Quantum (SFQ) First-in-First-Out (FIFO) Synchronizers: New Designs and Paradigms

Digital single-flux quantum (SFQ) technology promises to meet the demands of ultralow-power and high-speed computing needed for future exascale supercomputing systems. However, high degrees of variability makes ultrahigh-speed low-skew clock distribution of large-scale SFQ circuits challenging. This article proposes to mitigate this problem by supporting multiple independent SFQ clock domains with the design of reliable clock domain crossing (CDC) circuits. We first show that previously proposed CDC first-in-first-out buffers (FIFOs) are vulnerable to synchronization errors, motivating the need for more robust CDC FIFOs. Inspired by complementary metal-oxide-semiconductor (CMOS) multi-flip-flop FIFO synchronizers, we then present a metastability-resilient SFQ FIFO synchronizer that, simulations show, delivers over a 1000 reduction in logical error rate at 30 GHz. We show that, for a 10-stage FIFO, the Josephson junction area of our proposed design is only 7.5% larger than the nonresilient counterpart. Finally, we propose detailed design guidelines that define the minimal depth of our proposed synchronizers subject to both throughput and burstiness constraints.

Design and evaluation of dynamic partial reconfiguration using fault tolerance in asynchronous FPGA

In the recent past, the FPGA mechanism is a leading achievement medium for electronic digital circuit design. The digital systems are operated with both asynchronous and synchronous mode with multiple clocks. This paper presents fault tolerance to a grid of asynchronous clocked run time reconfigurable modules with dynamic and partially reconfigurable on FPGA. The fault tolerance of dynamic partial reconfiguration (DPR) model based on fault tolerance system in asynchronous clock operation model is implemented for FPGA. The proposed algorithm for DPR in the presence of faults uses the equalizer technique to eliminate the faults during the processing. The DPR reduces the runtime and memory space is saved by the partial reconfiguration in parallel computing of FPGA. The overall throughput of the development system is high for multiple clock domains within the grid. The performance of the proposed system is compared with the synchronous clocked grid system to prove the efficiency of the DPR. Experimental results show that the high efficiency and accuracy of the DPR with fault tolerance of FPGAs.

On SFC Low Power Hardware Implementation in FPGAs

The paper presents an idea of automatic synthesis to an FPGA device of a program developed with use of the SFC including actions. The synthesis is oriented to achieve power reduction by creating multiple clock domains and controlling switching activity. A circuit is selectively clocked based on processing activity. Global clock distribution networks are used in order to assure proper operation of a system. Proposed methods automatically split a controller into clock domains and implements all necessary circuitry. The paper is concluded with benchmark experiments that proves energy consumption reduction for proposed methods in reference to standard approach using fully synchronous implementation methodology.

Architecture and FPGA prototype of cycle stealing DMA array signal processor for ultrasound sector imaging systems

Array Signal Processor (ASP) is widely used in antenna-array beamforming applications, such as RADAR, SONAR, Medical Ultrasound, Multiple-Input-Multiple-Output (MIMO) etc. In this paper, architecture and Field Programmable Gate Array (FPGA) Prototype of a Cycle Steeling Direct Memory Access (DMA) Digital Beamformer (DBF) for Ultrasound Sector Imaging Systems is proposed. The architecture is based on delay and sum and it requires Fine Delay (FD) and Coarse Delay (CD) values to steer and dynamically focus the array, and apodization weights to improve the directivity. To improve the Fine delay accuracy Minimum Mean Square Error (MMSE) interpolation filter is proposed and implemented. To support wide Field of View (FOV) steering, immense delay values are required and real-time computations are hard for high sampling rate systems. Also, the precomputed delay values require huge memory, which causes a significant increase in the ASP area. To solve this problem, a cycle stealing DMA controller based on Quad Serial Peripheral (QSPI) interface to load delay values from external flash without disturbing ASP processing has been proposed and realized. Moreover, for debuggability,the architecture supports custom JTAG debug interface logic and lock-up latch based Design for Testability (DFT) Scan chain for multiple clock domains. The paper also presents the design and implementation of an Ultrasound Sector Imaging System Prototype setup to emulate the ASP. Most of the existing research work in this area supports ultrasound echo acquisition to PC and processing. However, the designed prototype helps researchers to validate computationally complex Ultrasound signal processing algorithms like ASP on FPGA and further processing on PC.

On the Analysis and the Mitigation of Power Supply Noise and Power Distribution Network Impedance Variation for Scan-Based Delay Testing Techniques

In this paper, we analyze the impact of the power supply noise and the power distribution network (PDN) impedance variation on the timing margin in both modes for ICs with multiple clock domains. We investigate the so-called intermodulation products (IMPs). We show that IMPs are mainly induced by the dependent nature of the transistors. We also provide experimental results showing that scan-based delay testing can be optimistic with respect to the mission mode for maximum achievable nominal frequency prediction, even at lower clock frequencies. We also show that IMPs can induce timing margin fluctuations that can be larger than that of the ones induced by the voltage droop in the test mode. Using an improved HSpice simulation model of a PDN validated by experimental results, we also quantify the timing margin variation due to power noise in the test mode as a function of the clock frequency, including the so-called clock stretching phenomenon. Finally, we propose a robust test signal scheme for multiple clock domain chips. The simulation results reveal that this scheme is less sensitive to PDN impedance variation than that of the most popular existing test schemes, and that it provides timing margins closer to those obtained in the mission mode.

A DVFS-aware cache bypassing technique for multiple clock domain mobile SoCs

A DVFS-aware cache bypassing technique for multiple clock domain mobile SoCs

A Study of 3-D Power Delivery Networks With Multiple Clock Domains

Ongoing advancements in 3-D manufacturing are enabling 3-D ICs to contain several processing cores, hardware accelerators, and dedicated peripherals. Most of these functional units operate with independent clock frequencies for power management reasons or simply for being hard intellectual properties. Thus, as diverse and heterogeneous circuits can be implemented on a 3-D IC, it also leads to the use of multiple clock domains. While these domains allow many functional units to run in parallel to exploit 3-D potentials, they also introduce power delivery challenges. This paper proposes an efficient analysis for assessing the worst case power supply noise on 3-D power delivery networks (PDNs) with multiple clock domains. This paper discusses power and thermal integrity issues that arise from multiple clock domains that share the same 3-D global PDN. We first examine power supply noise distribution on each tier and investigate scenarios that lead to worst case noise. Thermal analyses are also performed and heat distribution among clock domains and tiers is examined. In addition, the impact of clock domain structure and frequency on the overall power supply noise and temperature distribution has been quantified. Experiments show that the multiclock domains can induce excessive noise and the through-silicon-vias can contribute to power supply noise and heat transfer among tiers. This paper presents a summary of guidelines for modeling, analyzing, and exploring a design of reliable 3-D PDNs with multiple clock domains.

Variability in Multistage Synchronizers

System-on-a-chip designs typically employ multiple clock domains to interface several externally clocked circuits operating at different frequencies and to reduce power and area by breaking large clock trees into multiple small ones. The principal challenge of such globally asynchronous locally synchronous architectures is the need to reliably communicate between the different clock domains. To achieve high reliability margins in high-frequency designs implemented in modern process technologies, multistage synchronizers are often used. In this paper, we develop analytical formulas to calculate the probability of failure and the number of stages to use in such synchronizers. We compare our model with those reported in previous publications and show that most existing models underestimate mean time between failures (MTBF). Our model calculates an MTBF lower bound with significantly smaller margins. The concept of an effective resolution time constant for multistage synchronizers is introduced and the important effects of clock duty cycle and process variability are addressed. These process variability effects can be minimized by use of simple design rules for the synchronizer. For safety-critical applications, calculation of the probability of a failure-free lifetime for all products in a production run is developed and a simple lower bound is derived.

Eleven Ways to Boost Your Synchronizer

Synchronizers play an essential role in multiple clock domain systems-on-chip. The most common synchronizer consists of a series of pipelined flip-flops. Several factors influence the performance of synchronizers: circuit design, process technology, and operating conditions. Global factors apply to the entire integrated circuit, while others can be adjusted for each individual synchronizer in the design. The following guidelines are provided to improve synchronizers: avoiding scan and reset, selecting minimum size flip-flop cells, minimizing routing, reducing jitter in coherent clock domain crossings, opting for high-performance process flavor and minimum $V_{\rm TH}$ , over-provisioning to account for variations, maximizing supply voltage, and manipulating clock duty cycle.

A 22 nm 15-Core Enterprise Xeon® Processor Family

This paper describes a 4.3B transistors, 15-cores, 30-threads enterprise Xeon® processor with a 37.5 MB shared L3 cache implemented in a 22 nm 9M Hi-K metal gate tri-gate process. A modular floorplan methodology enables easy chops to 10 and 6 cores. Multiple clock and voltage domains are used to reduce power consumption. The clock distribution uses a single PLL per column to save power and minimize deskew crossing points. Integrated PCIe Gen3 and Quick Path Interconnect® (QPI) ports operate at 8GT/s. The 4-channel memory interface supports both 1866 MT/s DDR3 and a new memory buffer interface running at 2667 MT/s on the same pins. The core, cache and I/O recovery techniques improve manufacturing yields and enable multiple product flavors from the same silicon die.

An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design

In this paper, we first propose an HDR-mcd architecture, which integrates periodically all-in-phase based multiple clock domains and multi-cycle interconnect communication into high-level synthesis. In HDR-mcd, an entire chip is divided into several huddles. Huddles can realize synchronization between different clock domains in which interconnection delay should be considered during high-level synthesis. Next, we propose a high-level synthesis algorithm for HDR-mcd, which can reduce energy consumption by optimizing configuration and placement of huddles. Experimental results show that the proposed method achieves 32.5% energy-saving compared with the existing single clock domain based methods.

LOW POWER FRACTIONAL-N FREQUENCY DIVIDER WITH IMPROVED RESOLUTION

Multiple clock domain (MCD) systems have different blocks/IP cores operating at different frequencies. These different clocks are generated from a high frequency clock usually by integer division. Fractional-N frequency dividers (FFDs) are needed when the clock required by a block in MCD system is not possible to be derived by simple integer division. In this paper, we present such a FFD with an improved resolution of (1/8). Post layout simulation results after parasitic RC extraction in the 90-nm technology node show that our FFD is able to fractionally divide signals upto 2 GHz frequency with an average error of 0.11% in division ratio even with 2.5° phase error at the input. Our FFD consumes 754 μW when fractionally dividing a 2 GHz signal with a resolution of (1/8).

Mitigating the Impact of Process Variation on the Performance of 3-D Integrated Circuits

Three-dimensional die-stacking architectures have been proposed as a promising solution to the increasing interconnect delay that is observed in scaled technologies. Although prior research has extensively evaluated the performance advantage of moving from a 2-D to a 3-D design style, the impact of process parameter variations on 3-D designs has not been studied in detail. In this paper, we attempt to bridge this gap by proposing a variability-aware design framework for fully synchronous (FS) and multiple clock-domain (MCD) 3-D systems. To mitigate the impact of process variations on 3-D designs, we propose the variability-aware 3-D integration strategy for MCD 3-D systems that maximizes the probability of the design meeting specified system performance constraints. The proposed optimization strategy is shown to significantly outperform the FS and MCD 3-D implementations that are conventionally assembled, for example, the MCD designs assembled with the proposed integration strategy provide, on average, 44% and 16.33% higher absolute yield than the FS and conventional MCD designs, respectively, at the 50% yield point of the conventional MCD designs.

An On-Chip Test Clock Control Scheme for Circuit Aging Monitoring

In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. Aging can be monitored by performing a delay test at faster clocks than functional clock in field and checking the current delay state from the test clock frequencies at which the delay test is passed or failed. In this paper, we focus on test clock control scheme for a system-onchip (SoC) with multiple clock domains. We describe limitations of existing at-speed test clock control methods and present an on-chip faster-than-at-speed test clock control scheme for intra/inter-clock domain test. Experimental results show our simulation results and area analysis. With a simple control scheme, with low area overhead, and without any modification of scan architecture, the proposed method enables faster-than-at-speed test of SoCs with multiple clock domains.

Automated Verification and Clock Frequency Characteristics in CDC Solution

Recently, the design complexity of System-on-a-chip (SoC) has increased and additional functionalities have been added to SoC. Moreover, their operation clocks are frequently transferred from single clock domain to multiple clock domains. Because of the volume of the crossing signals and the variety methods of implementing crossed clock, the verification of clock domain crossings (CDCs) has become a very important and challenging task in deep submicron designs. Therefore, specialized CDC verification solutions can accurately detect CDC issues and efficiently debug the root causes of these problems that we require to perform design analyses. This paper describes certain case studies involving CDC verification and the relationship between clock and operating frequencies. Variable combination of clock frequencies rclk and wclk was evaluated for the asynchronous first-in first-out (FIFO) memory design. When a synchronizer was inserted, the power consumption decreased with the frequency; however, the performance achieved a dead point when wclk was about 1.3 times the value of rclk. The results confirmed that different combinations of clock frequency affected the circuit characteristics.

Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains

This article presents a hybrid Automatic Test Pattern Generation (ATPG) technique using the staggered Launch-On-Shift (LOS) scheme followed by the one-hot launch-on-shift scheme for testing delay faults in a scan design containing asynchronous clock domains. Typically, the staggered scheme produces small test sets but needs long ATPG runtime, whereas the one-hot scheme takes short ATPG runtime but yields large test sets. The proposed hybrid technique is intended to reduce test pattern count with acceptable ATPG runtime for multimillion-gate scan designs. In case the scan design contains multiple synchronous clock domains, and each group of synchronous clock domains is treated as a clock group and tested using a launch-aligned or a capture-aligned LOS scheme. By combining these schemes together, we found the pattern counts for two large industrial designs were reduced by approximately 1.6X to 1.8X, while the ATPG runtime was increased by 40% to 50%, when compared to the one-hot clocking scheme alone.

Area Efficient, High Speed EBCOT Architecture for Digital Cinema

Embedded block coding with optimised truncation (EBCOT) is a key algorithm in digital cinema (DC) distribution system. Though several high speed EBCOT architectures exist, all are not capable of meeting the DC specifications. To meet this challenge, the relationship between contents of a code block (CB) and context generation is studied. Our study reveals that it is difficult to predict number of contexts generated in a bit plane. Even the nature of number of contexts produced varies from CB to CB. In such a situation, it is difficult to ensure the frame rate requirement of DC. To avoid this uncertainty, a pass parallel, concurrent sample coding EBCOT architecture is proposed in this paper. It is capable of encoding one bit plane in 288 clock cycles under any circumstances. This design is prototyped on XC4VLX80-12 FPGA with multiple clock domains. After synthesizing, the bit plane coder (BPC) and MQ coder operate at 450 MHz and 123 MHz, respectively. In order to maintain synchronism among different clock domains, the BPC and MQ coder units are operated at 432 MHz and 108 MHz, respectively. This entails that the proposed design is capable of processing size 57 DC frames in a second.