Architecture and FPGA prototype of cycle stealing DMA array signal processor for ultrasound sector imaging systems

Abstract

Array Signal Processor (ASP) is widely used in antenna-array beamforming applications, such as RADAR, SONAR, Medical Ultrasound, Multiple-Input-Multiple-Output (MIMO) etc. In this paper, architecture and Field Programmable Gate Array (FPGA) Prototype of a Cycle Steeling Direct Memory Access (DMA) Digital Beamformer (DBF) for Ultrasound Sector Imaging Systems is proposed. The architecture is based on delay and sum and it requires Fine Delay (FD) and Coarse Delay (CD) values to steer and dynamically focus the array, and apodization weights to improve the directivity. To improve the Fine delay accuracy Minimum Mean Square Error (MMSE) interpolation filter is proposed and implemented. To support wide Field of View (FOV) steering, immense delay values are required and real-time computations are hard for high sampling rate systems. Also, the precomputed delay values require huge memory, which causes a significant increase in the ASP area. To solve this problem, a cycle stealing DMA controller based on Quad Serial Peripheral (QSPI) interface to load delay values from external flash without disturbing ASP processing has been proposed and realized. Moreover, for debuggability,the architecture supports custom JTAG debug interface logic and lock-up latch based Design for Testability (DFT) Scan chain for multiple clock domains. The paper also presents the design and implementation of an Ultrasound Sector Imaging System Prototype setup to emulate the ASP. Most of the existing research work in this area supports ultrasound echo acquisition to PC and processing. However, the designed prototype helps researchers to validate computationally complex Ultrasound signal processing algorithms like ASP on FPGA and further processing on PC.